Analog Design Manager

Job Description and Requirements

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You are technical first and a manager second—an experienced analog circuit designer with deep expertise in high-speed Multi-Gbps NRZ and PAM4 SerDes IP, including advanced process nodes such as FinFET and gate-all-around (GAA). You also have experience working with a small team as a team lead. You excel at translating SerDes standards into robust, high-performance circuit architectures and are skilled in transistor-level design, system budgeting, and analog/digital co-design.

You are proactive, analytical, and collaborative, with a strong ability to identify architectural bottlenecks and drive innovative solutions that improve silicon quality and reliability. As a technical leader and mentor, you value design excellence, knowledge sharing, and team growth. You are committed to continuous learning, diversity, inclusion, and delivering impactful results in a fast-moving, innovative environment.

You have led teams before. You know how to hire, grow senior leads, and set priorities when project deadlines must be met. At Synopsys, you will lead the design of flagship SerDes PHY IP that powers high-performance SoCs, while staying hands-on with the work.

What You’ll Be Doing

• Hands-on technical leadership: Lead a team of engineers working on the design of a major block, from specification through successful design review.
• Report to the analog project lead and ensure the design achieves optimal performance and power goals.
• People management: Lead a small team of analog design engineers who will report to you.
• Review SerDes standards and define transceiver architectures and analog sub-block specifications for high-speed NRZ and PAM4 IP.
• Help the team develop advanced circuit solutions to improve power, area, speed, and silicon robustness.
• Collaborate with digital and layout teams to ensure efficient design, verification, and implementation.
• Work closely with the layout team to optimize floorplans and physical layouts for optimal performance.
• Define and execute design and verification strategies using industry-standard simulation tools.
• Present technical results and design tradeoffs to internal teams, customers, and stakeholders.
• Document design features, test plans, and results clearly and accurately.
• Support electrical characterization, analyze customer silicon data, and contribute to post-silicon improvements.
• Assist the system team and develop automation to improve productivity and quality.

The Impact You Will Have

• Drive innovation in high-speed analog and mixed-signal design for next-generation connectivity, computing, networking, and AI.
• Influence SerDes architecture and improve scalability, performance, and power efficiency across the IP portfolio.
• Strengthen product quality and reliability through rigorous design, verification, and documentation.
• Lead and mentor team members while promoting a culture of technical excellence and continuous learning.
• Help deliver integrated solutions that meet demanding customer requirements and support successful post-silicon results.

What You’ll Need

• M.A.Sc. with 8+ years or PhD with 6+ years of relevant analog/mixed-signal IC design experience.
• 2+ years of experience in people management, including developing employees, hiring, and growing teams.
• Strong background in circuit/system modeling, analog design, DSP, and communications theory.
• Proven experience with Multi-Gbps SerDes architectures, including TX, RX, equalizers, samplers, drivers, serializers/deserializers, PLLs, DLLs, bandgaps, regulators, oscillators, ADCs, and DACs.
• Experience with analog/digital co-design, calibration, adaptation, and timing handoff.
• Familiarity with ESD design, custom high-speed digital logic, and reliability considerations such as EM, IR, aging, and self-heating.
• Proficiency in schematic entry, physical layout, SPICE simulation, and Verilog-A modeling.
• Strong understanding of jitter, noise, signal integrity, parasitics, crosstalk, and design-for-reliability principles.
• Excellent communication, documentation, problem-solving, and attention-to-detail skills.

Who You Are

• Collaborative, open-minded, and eager to learn from and support others.
• Analytical, detail-oriented, and committed to high-quality results.
• A clear communicator who can explain complex technical concepts effectively.
• Adaptable, resilient, and proactive in fast-paced environments.
• Dedicated to inclusion, innovation, and continuous improvement.

The Team You'll Be Part Of

You will join the Interface IP group in Mississauga, ON, a cross-functional team of analog and mixed-signal designers working on high-speed SerDes IP in the latest FinFET process nodes. The team operates with a full suite of industry-standard IC design tools supplemented by custom in-house automation supported by an experienced CAD and software team. This is a growing R&D organization focused on delivering SerDes IP that exceeds 200Gbps for networking, data center, and AI applications. You will collaborate closely with digital designers, verification engineers, layout specialists, and product engineering teams across Synopsys.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Synopsys Canada ULC values the diversity of our workforce. We are committed to provide access & opportunity to individuals with disabilities and will provide reasonable accommodation to individuals throughout the recruitment and employment process. Should you require an accommodation, please contact [email protected].