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Broadcom

Designs chips and software for data centers

Design Engineer - Timing Methodology

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeSan Jose, CA, USAIn-person

About the Job

Requirements

  • Typically, a Bachelor of Science degree in Electrical Engineering or Computer Science with 12+ years of industry experience, or a Master of Science or Ph.D. degree in Electrical Engineering or Computer Science with 10+ years of industry experience.
  • Strong hands-on experience in Timing Signoff methodology development and ownership.
  • Strong hands-on experience in SOC and 3D/2.5D IC timing signoff.
  • Strong hands-on experience with statistical data analysis and modeling.
  • Strong hands-on experience in silicon technologies, testability, and yield.
  • Strong hands-on experience with industry-standard STA tools such as PrimeTime and Tempus.
  • Strong hands-on experience developing scripts in TCL, Python, Perl, Unix shell, and flow automation.
  • Experience with revision control, issue management/defect tracking, continuous integration, and continuous delivery/deployment tools.
  • Ability to prioritize well, communicate clearly, proactively deliver practical and quality solutions on time, work well with external and internal partners, and possess advanced IC design engineering skills.
  • Ability to work across multiple facets of projects and handle multiple responsibilities at the same time.
  • Strong analytical skills; detail-oriented, organized, and methodical.
  • Strong communication skills, with the ability to be clear and concise.
  • Strong multitasking and context-switching skills.
  • Ability to ramp up quickly.
  • Ability to stay calm under extreme pressure.
  • Ability to work with minimum supervision, handle ambiguity, and drive problem solving to resolution autonomously.

Responsibilities

  • Develop and deploy timing signoff methodologies for advanced technology nodes.
  • Design and implement SOC, 3D/2.5D IC, and multi-die signoff solutions.
  • Participate in and lead EDA flow development for PrimeTime, Tempus, and Innovus.
  • Conduct advanced timing signoff methodology development and modeling for SOC and 3D/2.5D IC design, including complex studies and analysis of new concepts and the design, development, and improvement of existing and new solutions.
  • Work closely with experts across the company in a fast-paced, project-oriented agile environment.

About the Company

Broadcom

Designs chips and software for data centers

Broadcom designs chips and sells infrastructure software for the companies that run large data centers, telecom networks and corporate IT. Its custom AI processors, built with cloud companies, and its Ethernet switch chips move and process data inside the computer clusters that train AI models. The chip business also makes parts for broadband, wireless, storage and industrial equipment, sold to device makers and cloud operators, while VMware software lets businesses run private clouds and is sold by subscription. Broadcom took its current form in 2016, when Avago Technologies, formed in 2005 from Agilent's chip unit, bought Broadcom Corporation, and it is based in Palo Alto, California.

Company size
10,001+
Company stage
IPO
Headquarters
Palo Alto, CA
Founded
2005

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