ASIC Engineer - Ultra Low Latency

About the Position

We are looking to hire an experienced ASIC Engineer to help us design, test and deploy advanced hardware designs. As part of our Ultra Low Latency team, you’ll have the opportunity to collaborate with people in areas across the firm, including trading, networking and research infrastructure. We are looking for someone who can contribute to all of our projects and be happy to work on both FPGA-based and ASIC-based technologies.

We’re big believers in the ability of tools to improve the productivity, reliability and day-to-day joy of hardware engineering. That’s why we created Hardcaml, a hardware development toolchain embedded in OCaml. We don’t expect you to know OCaml (we’ll teach you here), but we are looking for hardware engineers who are excited about the advantages that better tools can bring, and are willing to try new things as a result.

About You

• 4+ years of practical experience in RTL design and verification, with a significant focus on ASIC design verification.
• Experience verifying ASIC designs using either Synopsys or Cadence tools.
• Experience applying software engineering techniques to improve the hardware design process and programming in high-level languages such as Python, C++, Java, or Haskell.
• Additional (preferred) experience in any of the following; formal verification, front-end RTL design and synthesis, or back-end physical design.

If you're a recruiting agency and want to partner with us, please reach out to [email protected].

Min salary: 250,000
Max salary: 300,000