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Leadership/Architect Role - DFT

THE ROLE:

As a Principal Member of Technical Staff (PMTS) in the IODC SoC DFT organization, you will lead end-to-end ATPG strategy, implementation, and pattern validation for complex, multi-million gate SoCs powering next-generation SOCs. You will be responsible for driving all ATPG execution activities from DFT architecture definition through pre-silicon verification, production test enablement, silicon bring-up, and manufacturing ramp.

This role requires close collaboration with RTL, DFT RTL, DFT Verification, Physical Design, Product Engineering Operations (PEO), ATE, and Silicon Validation teams to ensure high-quality test content, optimal coverage, tester readiness, and successful silicon deployment.

The ideal candidate combines deep technical expertise in ATPG, scan methodologies, and pattern validation with proven experience delivering production-quality test solutions for large-scale SoCs.

THE PERSON:

You are a highly motivated technical leader with extensive experience in SoC DFT and ATPG execution. You thrive in a fast-paced environment, enjoy solving complex debug challenges, and possess a strong track record of driving cross-functional execution from design conception through manufacturing.

You are comfortable working across multiple organizations, influencing technical direction, mentoring engineers, and serving as the key technical expert for ATPG signoff and silicon test readiness.

IMPACT

This role serves as the technical owner for ATPG execution across critical SoC programs and directly influences product quality, manufacturing yield, test cost, and time-to-market. The successful candidate will play a key role in enabling first-silicon success and scaling robust DFT methodologies across future AMD SoC generations.

KEY RESPONSIBILITIES:

Own end-to-end ATPG execution for large-scale SoCs from architecture phase through silicon production.
Define and drive ATPG methodologies, test strategies, coverage closure plans, and pattern signoff criteria.
Generate and validate scan, transition fault, cell-aware, bridge, chain diagnosis, and compression-based ATPG patterns.
Drive pattern quality improvements, tester efficiency optimization, and test cost reduction initiatives.
Partner closely with DFT RTL, DFT Verification, RTL, Physical Design, and Timing teams to ensure robust DFT implementation and testability.
Collaborate with PEO and ATE teams to enable tester bring-up, pattern correlation, tester debug, and manufacturing deployment.
Lead pattern validation activities across simulation, emulation, ATE, and platform environments.
Drive root-cause analysis and resolution of ATPG, tester, silicon, and yield-related issues.
Ensure high-quality pattern delivery meeting schedule, coverage, power, and manufacturing requirements.
Support silicon bring-up, diagnosis, yield learning, and production ramp activities.
Develop automation flows and AI-enabled solutions to improve ATPG productivity and debug turnaround time.
Mentor junior engineers and drive ATPG best practices across the organization.

PREFERRED EXPERIENCE:

16+ years of experience in SoC DFT with strong expertise in ATPG and manufacturing test.
Proven ownership of ATPG execution for multiple successful high-volume SoC products.
Extensive experience with multi-million gate SoCs and hierarchical ATPG methodologies.
Deep understanding of Scan, EDT/Compression, LBIST, MBIST, Boundary Scan, and DFT architecture.
Strong experience with pattern validation, tester correlation, and post-silicon debug.
Hands-on experience working with Product Engineering, Test Engineering, and ATE teams.
Experience debugging silicon failures and supporting yield improvement initiatives.
Strong scripting and automation skills using Python, Perl, Tcl, Shell, or similar languages.
Demonstrated ability to lead technical initiatives across geographically distributed teams.

PREFERRED TECHNICAL SKILLS

ATPG tools such as Tessent, Modus, TestMAX, TetraMAX, or equivalent.
Scan architecture, compression techniques, and diagnosis methodologies.
STIL, WGL, tester pattern formats, and pattern conversion flows.
Power-aware ATPG and test coverage optimization.
Pattern validation on simulation, emulation, ATE, and platform environments.
Silicon diagnosis, yield analysis, and failure characterization.
DFT timing, physical-aware ATPG, and implementation debug.
Strong knowledge of semiconductor manufacturing test flows and production test deployment.

ACADEMIC CREDENTIALS:

Bachelor’s or Master’s degree in related discipline preferred

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.

AMD

Leadership/Architect Role - Design for Test

About the Job

Requirements

Responsibilities

Desired Qualifications

IMPACT

PREFERRED TECHNICAL SKILLS

About the Company

AMD

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