Senior Physical Design Engineer

Responsibilities:

• All aspects of RTL to GDS2 physical implementation for complex ASIC projects.
• Working with Digital Design, Analogue Layout and DFT teams to ensure on time and high-quality results.
• Participating in project scoping and planning activities.
• Developing P&R methodologies for continuous improvement.

Required Skills and Qualifications:

• Bachelor's, Master’s or PhD degree in Electrical Engineering or related discipline and proven industry experience in a Physical Design position.
• Wide experience with industry standard EDA tools for digital implementation and signoff, and the ideal candidate should be familiar with:
• Synopsys Design Compiler and Primetime
• Cadence Innovus, Voltus and Conformal
• Hands-on working knowledge of deep sub-micron ASIC implementation and expertise in areas such as:
• RTL synthesis
• Timing constraint debug and development
• Floorplanning and power planning
• Clock tree synthesis
• P&R optimisation, timing closure and ECO implementation
• Static timing analysis
• Logical Equivalence Checks
• Power and EMIR analysis
• Proven responsibility for full design flow to design closure and tapeout.
• Knowledge of automating and advancing flows with proficiency in scripting.
• Ability to perform debug and analysis of designs, libraries, and technology files.
• Good communication and excellent collaboration skills.

This position is based in our Edinburgh office, UK. 

This is a hybrid position and will follow a 2+ day in-office work schedule, with in-office days based on business needs and team preference. You must be based within commutable distance of the work location listed on the job posting, or willing to relocate prior to beginning employment with Cirrus Logic.

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