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Architect Labs

AI-driven automated ASIC chip design platform

Member of Technical Staff – Research Intern

AI ResearchConfirmed live in the last 24 hours
InternshipPalo Alto, CA, USANo salary listedIn-person

About the Job

Requirements

  • Currently pursuing a PhD or Master's degree in Computer Science, Machine Learning, Mathematics, or a related field; exceptional undergraduates with strong research experience are also encouraged to apply.
  • Have strong academic understanding or project experience with Reinforcement Learning, such as PPO, DPO, or GRPO, and be comfortable reading and implementing concepts from recent research papers.
  • Have strong proficiency in Python and deep learning frameworks such as PyTorch, and be able to write clean, efficient research code.
  • Have experience with training or fine-tuning Large Language Models or familiarity with the modern natural language processing stack, including Transformers and HuggingFace.

Responsibilities

  • Co-design and implement Reinforcement Learning experiments, training data mixes, and reward signal explorations.
  • Contribute to research on post-training techniques and run ablation studies to improve model reasoning and alignment capabilities.
  • Implement and test new algorithms for model fine-tuning and evaluation, translating research papers into working prototypes.
  • Analyze experimental results and debug model behavior to help establish best practices for training recipes.

Desired Qualifications

  • Have previous internship experience at frontier AI labs or research organizations.
  • Have publications or submissions in top machine learning venues such as NeurIPS, ICLR, or ICML, or EDA venues such as DAC or ICCAD.
  • Have familiarity with hardware design concepts such as Verilog, RTL, or EDA tools.

About the Company

Architect Labs

AI-driven automated ASIC chip design platform

Architect Labs develops AI-powered tools to automate and speed up ASIC design for the semiconductor industry. It combines artificial intelligence with an integrated workflow for hardware exploration, SystemVerilog construction, verification, and physical design to produce end-to-end, verified chip designs. The platform aims to discover new architectures and generate ready-to-tute designs that are validated for modern machine learning workloads, enabling hardware/material co-optimization between AI models and specialized silicon. Compared to traditional EDA and ASIC design services, Architect Labs focuses on AI-guided architecture search, automated verification, and full-stack co-design to reduce time, cost, and labor in chip development. The goal is to shorten multi-year design timelines, lower upfront costs, and empower more specialized, high-performance silicon for data centers, automotive, robotics, and edge applications.

Company size
11-50
Company stage
Seed
Total funding
$24M
Headquarters
Palo Alto, CA
Founded
2025

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