Altera

FPGA and SoC provider with software

FPGA IP Software Development Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timeBengaluru, Karnataka, IndiaNo salary listedIn-person

About the Job

Requirements

A bachelor's or master's degree in Electronics Engineering, Electrical Engineering, VLSI, Embedded Systems, or a closely related technical discipline is required.
At least 7 years of dedicated experience writing production-grade RTL using SystemVerilog, Verilog, or VHDL is required.
Hands-on proficiency with FPGA vendor tool suites such as Altera Quartus Prime, AMD/Xilinx Vivado, or Microchip Libero is required.
Familiarity with static verification methodologies, including linting, clock domain crossing validation, and constraint troubleshooting, is required.
Ability to automate tool workflows using Tcl, Python, or shell scripting is required.

Responsibilities

Define micro-architecture and implement clean, efficient, reusable RTL code using SystemVerilog, Verilog, or VHDL.
Drive the FPGA tool flow, including synthesis, place-and-route, constraints creation, and static timing analysis.
Resolve multi-clock design issues, clock domain crossing anomalies, and timing violations.
Develop testbenches and run block-level behavioral simulations to debug and validate logic functionality before target implementation.
Validate RTL functionality on evaluation boards using lab equipment such as logic analyzers, oscilloscopes, and protocol compliance testers.
Collaborate with software and board-level hardware teams to establish specifications, interface architectures, and system integration paths.

Desired Qualifications

Familiarity with embedded SoC architectures such as ARM Cortex and RISC-V, and with hardware-software co-design.

Job Details:

Job Description:

Job Description

We are seeking a highly skilled and motivated Engineer to drive the architecture, development, and implementation of our Soft IP solutions. In this role, you will own the end-to-end FPGA Soft IP development lifecycle—from micro-architecture definition and RTL coding to timing closure, simulation, and physical hardware validation. You will work closely with embedded software, hardware, and systems engineering teams to deliver robust, high-performance FPGA Soft IP solution solutions.

Key Responsibilities

RTL Architecture & Coding: Define micro-architecture and implement clean, efficient, and reusable RTL code using System Verilog, Verilog, or VHDL.
IP Integration & Flow Management: Drive the full FPGA tool flow including synthesis, place-and-route (P&R), constraints creation, and static timing analysis (STA).
Timing Closure: Resolve complex multi-clock designs, Clock Domain Crossing (CDC) anomalies, and timing violations to ensure robust operation.
Verification & Simulation: Develop testbenches and run block-level behavioral simulations to thoroughly debug and validate logic functionality before target implementation.
Hardware Bring-up & Debug: Validate RTL functionality on actual evaluation boards using lab equipment like logic analyzers, oscilloscopes, and protocol compliance testers.
Cross-functional Collaboration: Collaborate with software and board-level hardware teams to establish specifications, interface architectures, and system integration paths.

Qualifications:

Required Qualifications & Technical Skills

Education: Bachelor’s or master’s degree in Electronics Engineering, Electrical Engineering, VLSI, Embedded Systems, or a closely related technical discipline.
Hardware Description: 7+ years of dedicated experience writing production-grade RTL using System Verilog, Verilog, or VHDL.
Toolchain Expertise: Hands-on proficiency with major FPGA vendor suites like Altera Quartus Prime, AMD / Xilinx Vivado or Microchip Libero.
Analysis & Linting: Strong familiarity with static verification methodologies including Linting, CDC validation, and constraint troubleshooting.
Scripting Skills: Ability to automate tool workflows using Tcl, Python, or Shell scripting.

Preferred / Bonus Skills

Familiarity with embedded SoC architectures (e.g., ARM Cortex, RISC-V) and hardware-software co-design.

Job Type:

Regular

Shift:

Shift 1 (India)

Primary Location:

Bengaluru, Karnataka, India

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

About the Company

Altera

FPGA and SoC provider with software

Altera designs and manufactures FPGAs and SoCs, along with software tools for hardware design and deployment. Customers can configure these programmable chips after fabrication to fit specific applications, helping them reach market faster and optimize performance. The company differentiates itself by offering a broad configurable silicon platform and a dedicated design software suite as an independent provider after its separation from Intel. Its goal is to deliver high-performance, adaptable processing solutions for industries like automotive, aerospace, communications, AI, cloud, and edge computing.

Company size: Not listed
Company stage: IPO
Headquarters: San Jose, CA
Founded: 1983

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