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Synopsys

EDA software for chip design

ASIC Digital Design Senior Staff Engineer

Hardware Validation & TestingUpdated on Nov 10
Full-timeBengaluru, Karnataka, IndiaNo salary listedIn-person

About the Job

Requirements

  • Four to eight years of hands-on experience in ASIC or RTL verification for IP cores or digital designs.
  • Understanding of verification planning, test case development, and coverage-driven verification concepts.
  • Working knowledge of UVM or similar verification methodologies, including building testbench components and writing test cases.
  • Solid SystemVerilog skills, including constrained-random verification, coverage, and assertions.
  • Familiarity with at least one industry-standard protocol such as MIPI UFS/UniPro, DDR, PCIe, Ethernet, or USB.
  • Experience debugging RTL simulations using waveform viewers and analyzing coverage reports to guide verification progress.
  • Experience with Perforce or a similar revision control environment.
  • Basic scripting ability in Python, Perl, Tcl, or shell scripting to support automation and regression management.
  • Ability to use AI tools such as Cursor and GitHub Copilot for analysis, development, debugging, and productivity.
  • Good communication, teamwork, and problem-solving skills.

Responsibilities

  • Build and maintain UVM-based testbenches for RTL IP cores, including agents, drivers, monitors, scoreboards, and coverage collectors.
  • Write SystemVerilog test cases and constrained-random stimulus to verify functional correctness across different operating modes and protocol scenarios.
  • Develop and execute verification plans based on design specifications, identifying test scenarios, corner cases, and coverage goals.
  • Debug RTL and testbench issues by analyzing simulation logs, waveforms, and coverage reports to isolate root causes and verify fixes.
  • Implement assertion-based checks and functional coverage models to track verification progress and ensure thorough validation.
  • Collaborate with design engineers to understand IP functionality, clarify requirements, and provide feedback on design-for-verification considerations.
  • Run regressions, analyze results, work toward coverage closure, and document verification status and outstanding issues.
  • Support the development of verification best practices and methodologies within the Bangalore team.

About the Company

Synopsys

EDA software for chip design

Synopsys provides software tools and services for electronic design automation (EDA), helping engineers design, simulate, verify, and optimize semiconductor chips and systems. Its products cover the full design flow, including RTL-to-gating synthesis, place-and-route, timing analysis, verification, and silicon validation, as well as software integrity solutions and hardware-assisted verification. Engineers use these tools to model, simulate, and validate complex chip designs before manufacturing, reducing bugs and improving performance. Compared with many competitors, Synopsys differentiates itself through its broad, end-to-end design toolchain, large ecosystem of IP and integration with simulation and modeling capabilities gained from its 2025 merger with ANSYS, and its global scale and support. The company aims to help designers push the boundaries of chip and system performance, accelerate time-to-market, and enable silicon-to-systems design across a wide range of industries.

Company size
10,001+
Company stage
IPO
Headquarters
Sunnyvale, CA
Founded
1986

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