Lead – Electrical Engineering - FPGA

Job Title: FPGA Design Engineer – Firmware Lead 
Job Code: 43345
Job Location: Rochester, New York
Job Schedule: 9/80 (Every Other Friday Off!)

Job Description: 
This position will lead FPGA Firmware Engineering activities in the Space Mission Systems (SMS) Segment of L3Harris.  The SMS Segment provides mission solutions for the space domain with defense, intelligence, and commercial applications.


Essential Functions: 
•    Support proposal efforts in the estimation and planning of end-to-end FPGA development.
•    Decompose and allocate system and box-level requirements to FPGA requirements and specifications.
•    Architect solutions against requirements and implement those solutions in various FPGA technologies or platforms. 
•    Lead small teams of engineers in executing FPGA development of highly reliable and robust FPGA designs.
•    Follow, enforce and refine consistent firmware development processes across FPGA designs.
•    Develop HDL code for module and top-level and generate appropriate testbench and verification environments
•    Map FPGA simulation work products to system-level requirements and capabilities.
•    Synthesize designs to targeted technologies and perform constraint driven place and route and timing analysis.
•    Ensure the FPGA simulations verify performance, then integrate and test the FPGA on the circuit card assembly.


Qualifications:  
•    Bachelor’s Degree and minimum 9 years of prior relevant experience. Graduate Degree and a minimum of 7 years of prior related experience. In lieu of a degree, minimum of 13 years of prior related experience.
•    Ability to obtain Federal Secret security clearance

Preferred Additional Skills: 
•    Secret or Top-Secret security clearance
•    Thorough understanding of VHDL, the FPGA design process, and the tools used to generate the FPGA designs
•    Thorough understanding of version control best practices and tools (subversion, git, etc.) to closely track changes to the FPGA baseline
•    Thorough understanding of the development of FPGA requirements and specifications
•    Designing for space environments
•    High speed memory interfaces
•    High speed serial protocols (PCI Express, SRIO, Ethernet)
•    Experience with Analog to Digital (AD) and Digital to Analog (DA) interfaces
•    Experience with control protocols such I2C, SPI, RS-232/422, and SpaceWire
•    Experience with complex block and top-level simulations of FPGA designs requiring high level transaction-based models
•    Self-motivated individual with the ability to work and communicate effectively within a development group
•    Proficiency with linting and CDC analysis tools
•    Proficiency with Xilinx, Microsemi, and Intel Tool Suites (VHDL, Synthesis, Place and Route, Simulation, Timing Analysis)

In compliance with pay transparency requirements, the salary range for this role in New York state is $110,500 - $205,500. This is not a guarantee of compensation or salary, as final offer amount may vary based on factors including but not limited to experience and geographic location. L3Harris also offers a variety of benefits, including health and disability insurance, 401(k) match, flexible spending accounts, EAP, education assistance, parental leave, paid time off, and company-paid holidays. The specific programs and options available to an employee may vary depending on date of hire, schedule type, and the applicability of collective bargaining agreements.
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In compliance with pay transparency requirements, the salary range for this role in New York state is $110,500 - $205,500. This is not a guarantee of compensation or salary, as final offer amount may vary based on factors including but not limited to experience and geographic location. L3Harris also offers a variety of benefits, including health and disability insurance, 401(k) match, flexible spending accounts, EAP, education assistance, parental leave, paid time off, and company-paid holidays. The specific programs and options available to an employee may vary depending on date of hire, schedule type, and the applicability of collective bargaining agreements.

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