Senior DFT Engineer

Job Description:

Are you in search for a new challenge? Are you equipped with forward looking spirit and experienced in digital design flows and tools? Design-for-Test (DFT) is a multi-disciplinary field of growing complexity which involves cooperation among multiple VLSI engineering skills, including design, architecture, verification, backend, timing, test, ATE and reliability and more. Take the opportunity and join us as a Senior DFT Engineer.

Presently we expand our Ukraine VLSI team. You'd be able to work on projects in one team with Ukrainian engineers. Our Senior stuff is open for knowledge sharing on a daily basis.

Your Role:

• DfT implementation inline with existing test methodology for advance process nodes;
• Perform top and/or block-level DFT insertion: scan compression, (i)JTAG, ATPG, patterns validation/simulation, MBIST/LBIST;
• Closely work with physical design team to resolve timing constraints/issues;
• Verify DFT circuitry and interface with other components/IPs and debug timing simulation issues;
• Debug and improve important DfT KPIs: test coverage/pattern efficiency;
• Hierarchical retargeting;
• Silicon bring-up, diagnosis and support for physical failure analysis.

Desired Qualifications:

• 5+ years of hands-on experience with DFT and test flows with commercial EDA tools for large and complex SOCs;
• Strong fundamental knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST/LBIST;
• Experience with one of the main EDAs providers: Synopsys DFT Complier, Tetramax, VCS, Tessent and Modus/Encounter tool suite;
• Experience in RTL simulation, synthesis, Linting, CDC and RDC checks, STA, DFT, quality metrics is a plus;
• Hands-on in Perl/Tcl/Python scripting;
• Excellent analytical, and problem-solving skills.

Skills:

Hierarchical DFT, DFT paritionning, ATPG, BIST, LBIS, Boundary scan, Memory Repair, Tap controler, Test coverage, IDDQ, HTOL, PVT corners. DFT strategy documentation. DFT architecture tradeoffs. DFT for chiplet. Wafer debug, yield management. DFT EDA Tools: Tessent, Testmax, test compressions, jtag. Support to product and Test Engineers.

What you will love about working here?

• We care about all our employees and want them to feel as comfortable as possible. That's why we offer health insurance from the first days, regardless of the probationary period.
• The Gift from the Company - Christmas holidays from December 25 to December 31.
• Cooperation with Superhumans center and Veteran HUB. Capgemini Engineering has supported the launch of psychological rehabilitation department of Superhumans. Our team also donated over UAH 500 000 prosthetics for three Ukrainian defenders. Currently, we support psychological counseling provided by the Veteran Hub, and we have implemented an internal policy making the company friendly to military and veterans with the assistance of the Hub.