Senior CAD and Methodology Design Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD. 

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. 

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

THE ROLE
As a design engineer in our CAD and methodology team, you will support and optimize the RTL-to-GDS design flow for the Project CAD team in the Adaptive & Embedded Computing Group (AECG). You will work across the complete RTL-to-GDS methodology — synthesis, place-and-route, and physical signoff — support tool deployments, and contribute to flow development across multiple semiconductor projects. You will help enable the tools, PDKs, and collateral the Silicon Development Team needs to operate efficiently, support the unified environment that sets tool, PDK, and design versions for chips in development, work with Silicon development teams requesting newer tool versions, and raise trouble tickets with CAD vendors as needed.

THE PERSON
You have a passion for modern, complex processor architecture, digital design, and physical implementation. You are a team player with excellent communication skills and experience collaborating with engineers across sites and time zones. You have strong analytical and problem-solving skills, and are eager to learn and take on new challenges.

KEY RESPONSIBILITIES

• Support the CAD infrastructure team on the RTL-to-GDS flow across multiple IC design projects
• Help maintain standardized RTL-to-GDS design flows and methodologies (synthesis → P&R → signoff)
• Implement and support customized RTL-to-GDS flows for Fabric design groups
• Work closely with external tool vendors to help the team meet design and development targets
• Develop tool-flow methodologies across the digital back-end — synthesis, place-and-route, and sign-off flows for timing, power, EM/IR, and DRC/LVS/DFM
• Improve engineering efficiency while improving design quality in the IP release process
• Support debug of bugs and issues across the RTL-to-GDS implementation flow
• Build flows in TCL and Python to ensure quality and faster execution
• Learn methodologies used across the industry to adopt best practices
• Leverage and deploy AMD AI systems to design teams

PREFERRED EXPERIENCE

• Fundamental programming and scripting skills (e.g., TCL, Python, PERL, or similar)
• RTL synthesis and place-and-route flows (Fusion Compiler / IC Compiler / Innovus or equivalent)
• Static timing analysis and constraints (PrimeTime / SDC)
• PDK and technology enablement
• Physical signoff: Calibre (DRC/LVS/DFM), extraction, and Totem/Redhawk for EM/IR
• Low-power (UPF) and power-integrity methodology
• Strong written and verbal communication skills

ACADEMIC CREDENTIALS

• Bachelor's or Master's degree in Computer Engineering / Electrical Engineering

LOCATION:

Penang, Malaysia

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Benefits offered are described:  AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.   We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position.  AMD’s “Responsible AI Policy” is available here.

This posting is for an existing vacancy.