Astera Labs

Designs chips that connect data center systems

Lead Firmware QA Engineer

Manual & Functional QA +1Confirmed live in the last 24 hours

Full-timeBengaluru, Karnataka, IndiaNo salary listedIn-person

About the Job

Requirements

A bachelor's degree in Electrical Engineering or Computer Science is required.
A master's or PhD in Electrical Engineering is preferred.
At least 4 years of experience is required.
Demonstrated experience as a PCIe switch test engineer and a solid understanding of the PCIe protocol are required.
Ability to estimate work, identify dependencies, and develop schedules is required.
Experience designing and executing functional, performance, interoperability, and stress tests is required.
Experience with manual and automated testing is required.
Strong Python scripting knowledge is required.
Experience performing signal integrity and protocol-level validation is required.
Experience triaging and debugging issues with development teams is required.
Experience collecting PCIe traces using a PCIe analyzer and analyzing traces to triage issues is required.
Experience with PRBS testing, loopback, and margining tests is required.
A good understanding of out-of-band testing and protocols such as MCTP, I2C, and SPDM is required.
Experience managing requirements and traceability through software development phases is required.
Experience using Git, Jira, and Confluence is required.

Responsibilities

Estimate work, identify dependencies, and develop schedules.
Design and execute functional, performance, interoperability, and stress tests.
Work closely with the silicon, architecture, and firmware development teams to understand designs and develop test strategies.
Perform manual and automated testing, including automation development.
Perform signal integrity and protocol-level validation.
Work closely with development teams to triage and debug issues.
Collect PCIe traces using a PCIe analyzer and analyze traces to triage issues.
Work regularly with hyperscalers and Tier 1 original equipment manufacturers to communicate plans and status, address escalations, and deliver on service-level agreements.
Manage requirements and traceability through software development phases.
Mentor and coach team members.

Desired Qualifications

Experience in PCIe compliance testing is a plus.
Knowledge of validating network interface card controllers and storage controllers is preferred.

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Title: Lead Firmware QA Engineer, Astera Labs, Bengaluru, India.

Astera Labs Inc., a leader in purpose-built connectivity solutions for data-centric systems, is seeking Lead Software QA Engineer for their Bengaluru (India) Design Center. Partnering with leading processor and GPU vendors, cloud service providers, world-class manufacturing companies, Astera Labs is helping data-centric system designers remove performance bottlenecks in compute-intensive workloads such as Artificial Intelligence and Machine Learning.

Basic Qualifications:

Bachelor’s degree in electrical engineering (EE) or Computer Science is required; a master’s or PhD in EE is preferred with minimum 4 years of experience.

Required Experience:

Experienced and detail oriented PCIe switch test engineer with solid understanding of PCIe protocol.
Estimate work, identify dependencies and develop schedules.
Responsible for designing and executing functional, performance, interoperability and stress tests.
Work closely with Silicon team, architecture team, FW development team to understand the design and develop test strategies.
Responsible for manual and automation testing.
Strong knowledge of scripting ( Python ) is must.
Responsible for automation development and manual testing.
Perform Signal integrity and protocol level validation.
Closely work with development teams to triage and debug issues.
Knowledge of collecting PCIe trace using PCIe analyzer and analyzing the trace to triage issues.
Experience in PRBS testing, loopback and margining tests.
Good understanding of OOB testing and Protocols like MCTP, I2C, SPDM etc.
Experience is PCIe compliance testing is a plus.
Regularly working with Hyperscale's and Tier 1 OEMs to communicate plans and status, address escalations, deliver on SLAs.
Knowledge in validation of NIC controllers and storage controllers is preferred.
Requirements management and traceability through software development phases.
Mentoring and coaching team members to help them excel in their jobs.
Power user of Git, Jira and Confluence.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

About the Company

Astera Labs

Designs chips that connect data center systems

Astera Labs designs chips and hardware modules that move data between processors, memory and accelerators in data centers. Its customers include cloud providers, chip vendors and equipment makers building servers and large computing clusters for AI and other workloads. Retimers restore signal quality, switches connect devices and memory controllers expand the memory available to computing systems, while COSMOS software monitors and manages these links. The company sells its products directly and through distributors, using outside manufacturers to fabricate and assemble its hardware. Astera Labs was founded in 2017 and is headquartered in San Jose, California.

Company size: 501-1,000
Company stage: IPO
Headquarters: San Jose, CA
Founded: 2017

Recently Posted Jobs

Explore more opportunities at Astera Labs

See more jobs