Real Communications

Senior Mixed Signal Design Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-timeSan Jose, CA, USANo salary listed

A Bachelor of Science or Master of Science degree in Electrical Engineering is required.
At least 3 years of experience designing CMOS analog or mixed-signal circuits is required.
In-depth understanding of deep-submicron CMOS processes and related circuit-design issues is required.
Familiarity with Cadence custom design tools, circuit simulators, and timing-analysis tools is required.
Fluency in English is required.

Design, simulate, and verify high-speed mixed-signal integrated circuits, particularly high-speed transceivers and high-frequency phase-locked loops.
Provide floorplan and layout guidelines for integrated-circuit layout engineers.
Provide practical silicon-package and printed-circuit-board layout guidelines for system-design engineers.
Participate in silicon measurement, characterization, and debugging.
Work within a cross-functional team.
Travel to Asia as needed.

A PhD is preferred.
Fluency in Mandarin Chinese is a plus.
Prior design experience with transmitters, receivers, clock-data recovery, and phase-locked loops for high-speed input/output interfaces is a plus.
Knowledge of system-level timing budgets, signal integrity, and power integrity is a plus.
Solid understanding of transmission-line and electromagnetic-wave theory is a plus.
Experience in printed-circuit-board layout and/or integrated-circuit package design is a plus.

• Design, simulate, and verify high-speed mixed-signal integrated circuits, in particular high-speed transceivers and high frequency PLLs

• Provide guidelines of floor plan and layout for IC layout engineers

• Provide practical guidelines for silicon package and PCB board layout for system design engineers

• Participate in measurement, characterization, and debugging of silicon

• Work within a cross-functional team

• Willing to travel to Asia.

• BS or MS in Electrical Engineering. PhD preferred.

• 3+ years' experience in design of CMOS analog / mixed-signal circuits

• In-depth understanding of deep submicron CMOS process and related circuit design issues

• Familiar with Cadence custom design tools, circuit simulator, and timing analysis tool

• Good communication skills, fluent in English and Mandarin Chinese is a plus

• Prior design experience in Tx, Rx, CDR, PLL for high speed IO interfaces is a plus

• Knowledge in system level timing budget, signal integrity, and power integrity is a plus

• Solid understanding of transmission line and EM wave theory is a plus.

• Experience in PCB layout and/or IC package design is a plus.

• Self-motivated quick learner, team worker

All your information will be kept confidential according to EEO guidelines.

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