Staff Digital Design Verification Engineer
E-Space
Staff Digital Design Verification Engineer
E-Space
Sustainable satellite constellations for AIoT data
HDL & Verification Methodology
· Strong proficiency in Verilog and SystemVerilog
· Experience writing tests within an existing UVM verification environment
· Solid understanding of UVM architecture and methodology
Programming & Scripting
· Ability to write C/C++ code for verification purposes
· Some scripting experience in Perl or Python
Verification Planning & Execution
· Ability to contribute to and help write test plans
· Experience writing and maintaining verification tests
· Ability to debug RTL simulations independently
Leadership
· Experience leading design verification efforts at the block level
· Experience driving code coverage closure on assigned blocks
6+ years of design verification experience in the semiconductor industry
E-Space designs small, easy-to-install satellite devices that can be tracked and connected from anywhere on Earth. Its E-Space LEO platform uses AIoT to optimize data from these devices, turning it into actionable insights and automated actions. By redesigning spacecraft, antenna, and deployment methods, it lowers the cost of satellite systems and makes space technology more accessible for governments, businesses, communities, and individuals. The company aims to be an ESG-aligned partner, using space data to support sustainable decisions and responsible planetary stewardship.
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