Physical Design Engineer
About the job
- Experience handling top-level complexity across floorplanning, placement, clock-tree synthesis, routing, and timing closure.
- Ability to take hard macros through place-and-route from netlist to GDS, including timing closure, formal verification, and physical verification.
- Experience with electronic design automation physical-design tools such as Cadence Innovus, Synopsys ICC2, PrimeTime SI, and Calibre.
- Expertise in physical-design implementation at advanced technology nodes, including floorplanning, macro placement, power-grid implementation, power routing, low-power implementation, place-and-route, static timing analysis, timing closure, clock-tree synthesis, low-power flows, and physical verification.
- Experience performing static timing analysis with PrimeTime SI, Tempus, or another industry-standard timing engine, including timing correlation, timing fixes, engineering-change-order generation, and corner/voltage definitions.
- Experience implementing custom or regular clock trees at block or top level, balancing complex trees, and reducing clock power.
- Knowledge of UPF/CPF flows and low-power implementation techniques.
- Experience running Calibre physical-verification checks, including design-rule checking, layout-versus-schematic, electrical-rule checking, and soft checks, with understanding of rules and fixes.
- Perform place-and-route experiments to validate new flows and methodologies for Adreno graphics cores.
- Perform physical implementation activities for the Adreno graphics processing unit team, including floorplanning, placement, clock-tree synthesis, routing, timing closure, low-power implementation, and physical verification.
- Perl, Python, or shell scripting experience for automation.
About the company
Mirafra Technologies delivers end-to-end ASIC and semiconductor engineering services from concept to silicon to system. It covers the full lifecycle—architecture, design, verification, physical implementation, packaging, embedded software, post-silicon validation, testing, and system solutions—with 2,200+ engineers and global delivery centers. The company positions itself as a one-stop partner, combining deep domain expertise with scalable software, AI, cloud, and data capabilities to support 50+ customers from startups to large tech firms. Its goal is to help customers speed time-to-market, reduce engineering complexity, and deliver next-generation semiconductor and intelligent system solutions with confidence.
Company Size
1,001-5,000
Company Stage
N/A
Total Funding
N/A
Headquarters
Bengaluru, India
Founded
2004
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Simplify's Take
What believers are saying
- Mirafra's February 2026 Normal Computing partnership expands AI-accelerated verification capabilities.
- Career postings on June 26, 2026 show demand across DFT, RTL, analog, and AI roles.
- The Munich launch and Taiwan presence strengthen access to European and foundry customer pipelines.
What critics are saying
- Ramanujan remains a demonstration vehicle; revenue concentration stays with services, not chips.
- Heavy hiring across 2026 signals talent dependence, and engineering attrition quickly hits delivery margins.
- Synopsys, Cadence, and larger Indian design houses compress pricing and poach senior semiconductor talent.
What makes Mirafra Technology unique
- Mirafra taped out Ramanujan, a 22-nm SoC at TSMC, on January 29, 2026.
- Mirafra sells end-to-end silicon delivery, from architecture through validation, not isolated staffing.
- Mirafra operates globally across Bengaluru, Austin, Munich, Taiwan, and multiple Indian design centers.
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