CPU Architecture Verification Engineer
NUVACORE
CPU Architecture Verification Engineer
NUVACORE
Designs high-performance, general-purpose CPU cores
Salary Range: 140000 to 250000 (Currency: USD) (Pay period: per-year-salary)
At NUVACORE we're designing a new general-purpose CPU core for the sustained, intensive demands of AI infrastructure and agentic computing, not the workloads of the past. We are seeking Verification Engineers at multiple levels — from Senior Engineer to Principal level — to help prove that the Nuvacore CPU is architecturally correct. As part of the design verification (DV) team, you will help drive architectural verification — checking the CPU's behavior and architectural state against the architecture specification and a golden reference model — building the stimulus, checkers, and flows that find architectural bugs long before silicon, working shoulder-to-shoulder with architecture and RTL design.
Plan & Strategy: Drive the verification scope, strategy, and test plans for architectural correctness — the CPU's behavior and architectural state versus the specification and a golden reference model.
Environment Setup: Build, maintain, and scale robust verification environments — including co-simulation against the golden reference model — that compare architectural state end to end.
Test & Debug: Generate stimulus in assembly and random instruction sequences (RIS) to exercise the full instruction set and architectural corner cases such as exceptions, interrupts, and privilege transitions.
Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the architectural test plan is complete.
Cross-functional Collaboration: Partner with architects and RTL teams to root-cause mismatches across RTL, model, and specification, drive design fixes, and support emulation, FPGA, and silicon bring-up.
Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design.
Strong knowledge of CPU architecture and micro-architecture — the instruction set, architectural state, exceptions, and privilege model — with a good understanding of at least one modern ISA (x86, ARM, or RISC-V).
Hands-on functional verification: test plans, testbenches, checkers, and coverage.
Proficiency in C/C++/Rust and/or SystemVerilog, plus a scripting language (Python; Perl a plus).
Experience writing and debugging tests in assembly for CPU verification.
Architectural / instruction-set verification against a golden reference model.
Random instruction sequence (RIS) stimulus generation.
Exceptions, interrupts, privilege levels, and virtualization.
Constrained-random verification and coverage-driven closure.
Assertions and formal verification.
Emulation/FPGA and silicon bring-up and debug (waveforms, trace).
Nuvacore designs high-performance, general-purpose CPU cores built from the ground up to meet AI-focused workloads in data centers and advanced systems. It offers cores as either IP for chip developers or finished chips, optimized for speed and area efficiency to handle continuous, long-running tasks. The team combines veterans from Nuvia, Apple, and Arm, focusing on agentic computing rather than specialized accelerators to differentiate from competitors. The goal is to deliver scalable, reliable CPUs that provide high throughput for large-scale AI workloads and continuous computing tasks.
Explore more opportunities at NUVACORE