DFT Engineer

Your Role

• Define SoC DFT architecture and strategy for subsystem and top-level designs.
• Establish ATPG, Scan, MBIST, and LBIST strategies.
• Drive test coverage objectives and ensure DFT quality requirements are achieved.
• Define test compression and diagnosis methodologies.
• Work closely with RTL, Verification, and Physical Design teams for DFT implementation and integration.
• Review and drive DFT sign-off requirements.
• Interface with customer test and manufacturing organizations for DFT-related requirements.
• Support DFT implementation from architecture through SoC tapeout.

Your Profile

• 12+ years of experience in DFT (Design for Test).
• Experience with multiple successful SoC tapeouts.
• Strong knowledge of RISC and ARM SoC DFT strategy for subsystems and top-level designs.
• Hands-on expertise in Scan Insertion and ATPG.
• Strong understanding of MBIST and LBIST.
• Hands-on experience with Tessent and/or Synopsys DFT tools.
• Good knowledge of test compression and diagnosis methodologies.
• Strong understanding of JTAG, IEEE 1500, and IEEE 1687.
• Experience in Safety DFT and automotive test methodologies is an advantage.
• Experience in silicon bring-up support, yield learning, and diagnosis is good to have.
• Knowledge of chiplet test architecture and advanced-node test challenges is an added advantage.
• Strong analytical, problem-solving, collaboration, and communication skills.

What You'll Love About Working Here

• We value flexibility and support our employees with hybrid work options and adaptable schedules to maintain a healthy work-life balance.
• Our inclusive culture brings together diverse professionals committed to growth, innovation, and excellence.
• At Capgemini, you can work on cutting-edge projects in technology and engineering with industry leaders and contribute to innovative semiconductor solutions.