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Micron Technology

Makes memory and storage chips for AI and PCs

NAND Custom Test Circuit Design Engineer

Silicon & ASIC DesignPosted on Nov 11
Full-timeSan Jose, CA, USAIn-person

About the Job

Requirements

  • A Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field, with at least 2 years of experience.
  • Hands-on experience in custom or analog circuit design, mixed-signal design, memory peripheral circuit design, or Product Engineering, with transistor-level circuit and silicon-debug exposure.
  • Strong understanding of CMOS device operation, transistor-level circuit design, leakage mechanisms, parasitics, PVT sensitivity, timing, loading, noise margin, power, and reliability principles.
  • Hands-on proficiency with circuit build entry, waveform debug, and post-layout verification.
  • Proficiency with XA or equivalent fast transistor-level simulation, Verilog, and mixed-signal validation methodologies.
  • Understanding of Design for Test and Design for Manufacturing methodologies, including fault models and coverage metrics, scan or built-in self-test concepts, test-point insertion, automatic test pattern generation awareness, statistical variation and Monte Carlo analysis, process-window and yield optimization, redundancy or repair strategies, and wafer/package test cost trade-offs.
  • Proficiency in Python and scripting for simulation automation, regression analysis, result extraction, waveform processing, and engineering efficiency.
  • Ability to identify workflows that can be improved through AI, develop or adapt AI-enabled engineering solutions, and apply appropriate technical review, data protection, and engineering judgment.

Responsibilities

  • Develop, integrate, and optimize custom test circuit architectures for NAND flash memory designs, including transistor-level digital, analog, mixed-signal, monitoring, control, and memory-array interface circuits.
  • Interpret product specifications and test requirements; define circuit functionality, interfaces, operating limits, controllability, observability, and validation criteria.
  • Create, review, and optimize schematics, device sizing, bias structures, sensing and monitoring paths, and multiplexers relevant to test circuits.
  • Analyze circuit testability and robustness to ensure compliance with quality, coverage, manufacturability, power, area, and reliability requirements.
  • Drive Design for Test requirements for custom NAND test circuits, including controllability and observability, test-mode architecture, fault coverage, built-in self-test and diagnostic access where applicable, and automatic test pattern generation or pattern-generation interfaces; partner with Product Engineering and test teams to close coverage gaps and enable efficient wafer and package testing.
  • Apply Design for Manufacturing principles to improve process-window margin, yield, and high-volume manufacturability through PVT and Monte Carlo analysis, mismatch and variation assessment, layout-aware design rules, redundancy or repair considerations, and silicon-data-driven optimization.
  • Validate custom test circuits using XA simulations, Verilog simulations, and mixed-signal validation environments.
  • Collaborate with layout teams on matching, parasitic sensitivity, shielding, routing, guard rings, device placement, and layout-dependent effects; review post-layout results and drive closure.
  • Evaluate circuit risks, including leakage, contention, floating nodes, device overstress, power sequencing, current density, electromigration/IR drop, and long-duration stress conditions.
  • Create and debug test sequences and test modes required to control, observe, characterize, and validate custom test circuits at wafer and package levels.
  • Work with Product Engineering during first-silicon bring-up, debug and characterization, failure isolation, simulation-to-silicon correlation, and ramp to high-volume production.
  • Use laboratory measurements and silicon data to identify root cause and recommend circuit, test-mode, characterization, or screening improvements.
  • Apply a Design + AI approach as a core responsibility by using AI-assisted and agentic engineering workflows to accelerate circuit review, simulation triage, waveform analysis, root-cause investigation, automation, documentation, and knowledge retrieval while maintaining engineering rigor and sign-off subject-area expertise.
  • Develop Python- or scripting-based automation and AI-enabled solutions that improve design quality, reduce turnaround time, and increase engineering efficiency.
  • Document test-circuit methodologies, specifications, design decisions, validation results, silicon correlation, and clear technical recommendations.

About the Company

Micron Technology

Makes memory and storage chips for AI and PCs

Micron Technology designs and manufactures memory and storage chips, mainly DRAM and NAND flash, used in data centers, PCs, phones, cars and industrial equipment. It is one of only three companies that make HBM, the stacked high-bandwidth memory placed beside processors in AI servers, and it is the largest memory chipmaker based in the United States. Unlike chip designers that outsource production, Micron runs its own fabs and assembly sites in the United States and across Asia. It earns money by selling chips, memory modules and solid-state drives to cloud providers, device makers and distributors. Micron was founded in 1978 and is headquartered in Boise, Idaho.

Company size
10,001+
Company stage
IPO
Headquarters
Boise, ID
Founded
1978

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