Design Verification IP Lead

<strong>Job Requirements </strong><br><p>The <strong>IP DV Lead</strong> is a "deep-diver." This role focuses on the exhaustive verification of a specific functional block (e.g., a Crypto engine, Video Codec, or High-Speed Controller), ensuring 100% functional and code coverage within that domain.</p><p><strong>Core Responsibilities</strong></p><p><strong>Block-Level Strategy:</strong> Create comprehensive testplans based on IP functional specifications to reach 100% functional coverage.</p><p><strong>Environment Development:</strong> Build highly constrained-random UVM environments, including agents, monitors, and complex scoreboards.</p><p><strong>Formal Verification:</strong> Apply formal methods (SVA) to verify complex state machines or data paths where simulation falls short.</p><p><strong>Bug Hunting:</strong> Identify corner-case bugs through assertions and functional coverage-driven stimulus.</p><p><strong>Regression Management:</strong> Maintain high-efficiency regression suites and lead the closure of code, functional, and toggle coverage.</p><p><strong>Collaboration:</strong> Work closely with RTL designers to resolve architectural ambiguities and debug RTL failures.</p><p><strong>Required Skills & Qualifications</strong></p><p><strong>Experience:</strong> 8+ years in IP-level functional verification.</p><p><strong>Technical Mastery:</strong> Advanced <strong>SystemVerilog/UVM</strong> and expertise in writing complex <strong>SVA (SystemVerilog Assertions)</strong>.</p><p><strong>Domain Expertise:</strong> Specific knowledge of the IP being verified (e.g., USB, Ethernet, or AI accelerators).</p><p><strong>Methodology:</strong> Strong background in Constrained Random Verification (CRV) and coverage-driven sign-off.</p><p><strong>Scripting:</strong> Proficiency in Python or Perl for testbench automation and log parsing.</p><br><br>