Capgemini

Global consulting, technology services, outsourcing

Senior Physical Design Engineer

Silicon & ASIC DesignUpdated on Nov 14

Full-timeNo salary listedIn-person

About the Job

Requirements

At least 8 years of challenging RTL-to-GDSII work on 10 nm or below process nodes with designs containing 500,000 to 1 million or more instances.
Strong proficiency with place-and-route and timing-analysis computer-aided design tools from Synopsys and/or Cadence.
Good knowledge of synthesis flow, scan insertion and coverage, and optimization.
Excellent skills in floorplanning, power planning, clock-tree synthesis, placement, routing, and timing closure.
Proficiency in Perl, Tcl, Python scripting, and Makefile.
Expertise in static timing analysis and PrimeTime SI, signal-integrity closure, and engineering change order generation and implementation.
Excellent skills in electromigration/IR-drop, design-rule-check, layout-versus-schematic, and electrical-rule-check analysis and fixes.
Experience with sign-off and tape-out closure work.

Responsibilities

Manage all aspects of physical design at full-chip or block level in advanced technology nodes of 10 nm and below.
Perform floorplanning, partitioning and budgeting, power-mesh distribution, clock-tree planning and analysis, scan reordering, placement, clock-tree synthesis, and place-and-route.
Perform timing-analysis activities through sign-off, including signal-integrity and noise closure, and complete functional and timing engineering change order tasks.
Lead validation and qualification activities, including formal verification, electromigration/IR-drop, design-rule-check, layout-versus-schematic, antenna, and electrical-rule-check analysis and fixes.
Contribute to developing and implementing the overall low-power solution.
Develop and enhance timing-related scripts for clock-skew analysis, critical-path analysis, input/output interfaces, and constraints partitioning and budgeting from top level to block level.
Complete multiple high-complexity design cycles with limited supervision.

Desired Qualifications

Experience with top-level floorplanning, pin assignment, and tape-out activities.

Your role

Responsible for all aspects of Physical Design in full chip or block level in extremely advanced technologies nodes (10nm and below)
In deep Floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, Scan re-ordering, placement, CTS, place and route.
Cover all relevant activities related to timing analysis (closure through sign-off including SI/noise) ECO tasks (both functional and timing)
In charge with all validation/qualification tasks : Formal Verification, EM/IR, DRC, LVS, Antenna, ERC analysis and fixes
Be part of the overall Low Power solution development and implementation
Develop/enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from toplevel to block level)
Complete multiple design cycles of high complexity with little supervision

Desired qualifications/skills

8+ years in challenging RTL2GDSII work done on 10nm or below nodes with 500k –1million+ instances in designs
Power user of PnR and timing analysis CAD tools from Synopsys and/or Cadence
Good knowledge of synthesis flow, insertDFT scan/coverage and optimization
Excellent floorplan, power plan, CTS, place, route, and timing closure skills
Proficiency using Perl/TCL/Python scripting and Makefile
Expertise in timing STA/PTSI – signal integrity closure, ECO generation/implementation skill
Excellent EM/IR, DRC, LVS, ERC analysis and fixing skills
Experience with sign-off tape-out closure work
Any top level – floor planning, pin assignment – tape out activities is a plus

We offer

Competitive Salary & Benefits
Respect for your private life and your choices
All tools required for high performance in your field
Responsible approach, long-term commitments, and stability

About the Company

Capgemini

Global consulting, technology services, outsourcing

Capgemini provides consulting, technology services, and outsourcing to help organizations transform digitally. Its offerings include strategy and transformation consulting, system integration, application development, IT infrastructure management, and managed IT operations. It differentiates itself with a global presence in over 50 countries and a focus on applying AI, cloud, and cybersecurity to real business problems. Its goal is to help clients navigate digital transformation and improve efficiency and innovation through tailored, contract-based or managed services.

Company size: 10,001+
Company stage: IPO
Headquarters: Paris, France
Founded: 1967

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