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AMD

Designs chips for computers and AI systems

ASIC Front-End Methodology Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeHyderabad, Telangana, IndiaNo salary listedIn-person

About the Job

Requirements

  • Strong experience in ASIC front-end implementation methodologies and electronic design automation tool flows.
  • Experience managing tool versions, methodology releases, rulesets, and multi-project flow deployments.
  • Understanding of RTL-to-GDS implementation flows, including synthesis, constraints, clock-domain crossing, lint, design for test, static timing analysis, and physical design interactions.
  • Experience working across multiple IPs, subsystems, chiplets, or SoC programs with methodology governance responsibilities.
  • Experience developing automation, scripting, dashboards, or artificial intelligence-enabled solutions for flow management and quality improvement.
  • Familiarity with configuration management systems, regression infrastructure, release processes, and tool qualification methodologies.
  • Experience defining methodology standards, signoff requirements, and best practices for large-scale ASIC programs.
  • Excellent written, verbal, presentation, and customer-facing communication skills.
  • Ability to influence stakeholders and drive alignment across geographically distributed teams.
  • A Bachelor's degree with 8+ years of experience, or a Master's degree with 6+ years of experience, in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Demonstrated experience in ASIC front-end methodology, CAD flow development, or large-scale SoC implementation environments.
  • Strong leadership and collaboration mindset.
  • Passion for methodology development, standardization, and continuous improvement.
  • Interest in AI/ML-driven productivity solutions, automation, and next-generation design methodologies.
  • Ability to effectively communicate and influence both technical and non-technical stakeholders.
  • Experience working directly with internal customers and cross-functional executive stakeholders.

Responsibilities

  • Own and drive front-end methodology alignment across multiple chiplets, subsystems, and SoC programs.
  • Manage tool qualification, deployment, version control, and migration strategies across projects.
  • Develop, maintain, and govern front-end flow infrastructure, methodology guidelines, and design rulesets.
  • Partner with CAD teams to evaluate, deploy, and support new methodologies, electronic design automation tools, and automation solutions.
  • Coordinate with Design, Physical Design, DFT, Verification, and Architecture teams to ensure methodology requirements are understood and implemented consistently.
  • Identify flow gaps, integration issues, and methodology risks early, and drive closure plans across stakeholders.
  • Define and track methodology compliance metrics, quality indicators, and readiness criteria.
  • Drive root-cause analysis for flow-related issues and implement long-term solutions to improve execution efficiency and quality.
  • Lead cross-functional technical reviews, alignment meetings, and customer-facing discussions related to methodology, flow readiness, and tool deployment.
  • Mentor engineers and provide technical leadership for methodology adoption and best practices.

About the Company

AMD

Designs chips for computers and AI systems

AMD designs processors, graphics chips and AI accelerators for computer makers, cloud operators and businesses that build electronic devices. Its Ryzen processors power personal computers, while EPYC processors handle work in data centers and Radeon chips render graphics. Instinct accelerators run AI models, paired with software that developers use to train models and put them into production. AMD sells chips and related computing systems through equipment makers, distributors and retail channels, and contracts with outside foundries to fabricate its semiconductor designs. It was founded in 1969 and has its headquarters in Santa Clara, California.

Company size
10,001+
Company stage
IPO
Headquarters
Santa Clara, CA
Founded
1969

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