NUVACORE

Designs high-performance, general-purpose CPU cores

CPU Custom Library and Memory Layout Lead

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-time$200k - $300k /yr

About the Job

Requirements

Hold a Bachelor of Science or Master of Science degree and have 12 or more years of experience in custom or standard-cell and/or memory layout at advanced CMOS nodes.
Have hands-on transistor-level layout experience with static circuits and state-retaining elements, including latches and flip-flops, as well as memory arrays such as bit cells, sense amplifiers, and decoders at advanced CMOS nodes.
Have deep knowledge of design rule checking, layout-versus-schematic, antenna rules, parasitic extraction, and layout-versus-schematic closure using industry-standard electronic design automation tools such as Virtuoso, Calibre, and StarRC.
Have a strong understanding of layout-dependent effects, matching and symmetry techniques, and their impact on circuit performance, power, area, and variation.
Have experience providing layout-driven feedback to foundry partners on performance, power, area, yield, and design rule checking/process design kit improvements.
Have relevant hands-on experience laying out designs in cutting-edge process technologies; Gate-All-Around nodes are preferred.
Have strong communication and collaboration skills and be comfortable working directly with circuit design, foundry, and computer-aided design partner teams.

Responsibilities

Lead physical layout of custom library cells, including flip-flops, clock-gating cells, level shifters, and AOI cells, and custom memory arrays, including bit-cell arrays, sense amplifiers, decoders, and register files, at advanced process nodes; own layout prototyping of critical cells.
Own end-to-end layout closure, including floorplanning, logic and SRAM place-and-route, design rule checking/layout-versus-schematic/antenna clean-up, parasitic extraction hand-off, and mitigation of layout-dependent effects.
Partner with circuit design, foundry/process design kit, computer-aided design, and design-for-test teams to co-optimize layout for performance, power, area, manufacturability, and yield; validate intellectual property on test chips.
Define and drive layout methodology and automation, including P-cell/script-based layout generation and design rule checking/layout-versus-schematic regression, to improve design efficiency and establish team-wide best practices.
Manage layout vendors and contractors to scale layout execution across macro designs and cells by scoping work packages, setting quality and schedule targets, and reviewing deliverables for performance, power, area, design rule checking/layout-versus-schematic, and methodology compliance.

Desired Qualifications

Have experience across the full custom layout flow, including floorplanning, cell/bit-cell layout, P-cell/script-based automation, design rule checking/layout-versus-schematic signoff, and extraction hand-off.
Be proficient in SKILL, Python, or Tcl to build and improve layout automation and design rule checking/layout-versus-schematic regression flows.
Have a track record of delivering production-level standard cell and/or memory layouts through tape-out, with silicon-validated performance, power, and area in high-volume products.
Have experience with test-chip layout development and design-technology co-optimization partnering with foundries at leading-edge nodes.
Have experience managing external layout vendors/contractors, including work scoping, quality/schedule tracking, and technical review, to scale capacity across macro and cell layout programs.
Have experience using agentic artificial intelligence tools for productivity and automation.

Salary Range: 200000 to 300000 (Currency: USD) (Pay period: per-year-salary)

At NUVACORE we're designing a new general-purpose CPU core for the sustained, intensive demands of AI infrastructure and agentic computing, not the workloads of the past. As a member of the CPU-specific custom circuit design team, you will enable the design to achieve the target PPA specifications for the product.

THE ROLE

As a Custom Library and Memory Layout Lead, you will participate in the following :

Lead physical layout of custom library cells (flip-flops, clock-gating cells, level shifters, AOI cells) and custom memory arrays (bit cell arrays, sense amps, decoders, register files) at advanced process nodes - own layout prototyping of critical cells.
Own end-to-end layout closure: floorplanning, logic/SRAM place-and-route, DRC/LVS/antenna clean-up, parasitic extraction hand-off, and mitigation of layout-dependent effects (LDE).
Partner with circuit design, Foundry/PDK, CAD, and DFT teams to co-optimize layout for PPA, manufacturability, and yield; validate IP on testchips.
Define and drive layout methodology and automation — including P-cell/script-based layout generation and DRC/LVS regression — to raise design efficiency and set team-wide best practices.
Manage layout vendors and contractors to scale layout execution across macro designs and cells — scoping work packages, setting quality/schedule targets, and reviewing deliverables for PPA, DRC/LVS, and methodology compliance.

MINIMUM QUALIFICATIONS

Hold a BS or MS degree with 12+ years of experience in custom/standard-cell and/or memory layout at advanced CMOS nodes.
Hands-on transistor-level layout experience with static circuits and state-retaining elements (latches, flops), as well as memory arrays — bit cells, sense amps, decoders — at advanced CMOS nodes.
Deep knowledge of DRC/LVS/antenna rules, parasitic extraction, and layout-versus-schematic closure using industry-standard EDA tools (e.g. Virtuoso, Calibre, StarRC).
Strong understanding of layout-dependent effects, matching and symmetry techniques, and their impact on circuit PPA and variation.
Experience providing layout-driven feedback to foundry partners on PPA, yield, and DRC/PDK improvements.
Strong communication and collaboration skills, comfortable working directly with circuit design, foundry, and CAD partner teams.
Relevant hands-on experience laying out designs in cutting-edge process technologies, preferably Gate-All-Around (GAA) nodes.

REQUIREMENTS — PREFERRED

Experience across the full custom layout flow — floorplanning, cell/bit-cell layout, P-cell/script-based automation, DRC/LVS signoff, and extraction hand-off.
Proficient in SKILL, Python, or Tcl to build and improve layout automation and DRC/LVS regression flows.
Track record delivering production-level standard cell and/or memory layouts through tape-out, with silicon-validated PPA in high-volume products.
Experience with testchip layout development and DTCO partnering with foundries at leading-edge nodes.
Experience managing external layout vendors/contractors — work scoping, quality/schedule tracking, and technical review — to scale capacity across macro and cell layout programs.
Experience using Agentic AI tools for productivity and automation.

The next great CPU won't build itself. We’re assembling a world-class team across every layer of CPU development, from architecture and design to verification, physical implementation, software, infrastructure, and product delivery. Every discipline matters, and every person has the opportunity to help shape the technology from the ground up.

About the Company

NUVACORE

Designs high-performance, general-purpose CPU cores

Nuvacore designs high-performance, general-purpose CPU cores built from the ground up to meet AI-focused workloads in data centers and advanced systems. It offers cores as either IP for chip developers or finished chips, optimized for speed and area efficiency to handle continuous, long-running tasks. The team combines veterans from Nuvia, Apple, and Arm, focusing on agentic computing rather than specialized accelerators to differentiate from competitors. The goal is to deliver scalable, reliable CPUs that provide high throughput for large-scale AI workloads and continuous computing tasks.

Company size: 51-200
Company stage: Not listed
Total funding: Not listed
Headquarters: San Jose, CA
Founded: 2026

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