Compute Interconnect IP Planner

Job Details:

Job Description:

About Altera

At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely—empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role

The Altera FPGA Intellectual Property (IP) portfolio includes a comprehensive breadth of hard (silicon) and soft (configurable logic) IP for our Field Programmable Gate Array (FPGA) semiconductor devices. This Planner / Product Manager position is focused on Compute Interconnect such as PCI Express (PCIe), Compute Express Link (CXL), Ultra Accelerator Link (UALink), Coherent Hub Interface (CHI), along with Direct Memory Access (DMA) IP.

Come join a team responsible for making decisions that have a global and long-lasting impact on the company. In this role you will analyze and synthesize requirements from various sources including Altera’s product roadmap, competitive solutions, marketing and business development teams, sales/field/support teams, and customers. You’ll work closely with engineering architecture and execution teams to ensure that all requirements and feature specifications are well defined and prioritized, to drive the delivery process and timeline for hard and soft IP.

Responsibilities:

• Drive the definition, trade-off analysis, and convergence of next-generation hard and soft IP solutions that enable various FPGA end markets and applications

• Coordinate with business stakeholders and customers to continuously drive market requirements into the product definition and solutions roadmap

• Generate specific product requirements

• Maintain and communicate a detailed IP product roadmap

• Coordinate with peers to align interdependent programs and solutions

• Manage and track input to engineering execution and change management processes

Desired Competencies:

• Business acumen – understanding of business and technical challenges and landscape

• Leadership – ability to define, influence, and drive decisions proactively

• Presence and Communications – ability to facilitate engagement and open communication in stressful situations, articulate ideas and concepts to promote change, and communicate goals and plans to executive staff and critical project stakeholders

• Strong interpersonal skills – willingness to speak up to ensure success of program, understand the diverse perspectives of stakeholders and work with them to resolve differences

• Initiative – comfort driving unchartered, high-paced programs in a dynamic team environment

• Strong analytical skills – data-driven and detailed with strong problem-solving skills, ability to structure complicated issues and find creative solutions to business challenges

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$149,100 - $215,925 USD

We use artificial intelligence to screen, assess, or select applicants for the position.  Applicants must be eligible for any required U.S. export authorizations.

#LI-MD1

Qualifications:

Minimum Qualifications:

• Bachelor’s degree or equivalent in Electrical Engineering, Computer Science, Computer Engineering, or other related field of study

• 10+ years of experience in FPGA applications, IP, or related server, storage, data center, and/or acceleration domains with expertise in Compute Interconnect IP such as PCIe, CXL, UALink, CHI, or DMA.

Preferred Qualifications:

• Technical depth and understanding of semiconductor IP solutions for FPGA or ASIC

• Technical depth and understanding of FPGA development tool flows and solutions

• Direct experience in architecting FPGA-based solutions for an end market/application

• Industry knowledge of dynamics, trends, success factors, and competitive forces in FPGA end markets/applications

• Experience in a customer-facing and engagement role

• Relevant product planning/management or technical marketing experience

Job Type:

Regular

Shift:

Shift 1 (United States of America)

Primary Location:

San Jose, California, United States

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.