Extensive experience in low-latency applications and video intellectual property.
Candidates with ASIC tape-out experience should indicate it and apply to the ASIC / Physical Design Engineer role.
Responsibilities
Develop FPGA solutions for low-latency applications and video intellectual property.
Work hands-on on novel problems without established solutions.
Iterate quickly and support frequent tape-outs, with each silicon spin improving on the previous one.
DiffLogic is on a mission to end matrix multiplication. We don't run models on chips. We build chips that are the model. That means tape-out isn't a milestone. It's the product. We iterate fast, we tape out frequently, and every spin ships smarter silicon than the last.
We're hiring exceptional FPGA engineers, with extensive experience in low-latency applications and Video IP. You'll work on questions that don't yet have established solutions, and most have never been asked outside this lab. And you will not simply redevelop yet another variation of existing solutions. Everyone here is hands-on and moves fast.
If you also have ASIC tape-out experience, please indicate it, and apply to "ASIC / Physical Design Engineer”.