Verification Engineering Lead/Manager
About the job
- A Bachelor of Science in Electrical Engineering with at least 8 years of experience, or a Master of Science in Electrical Engineering with at least 6 years of experience.
- Knowledge of at least one high-speed interface such as USB, MIPI, PCIe, Ethernet, or DisplayPort.
- Knowledge of two or three peripheral interfaces such as SDIO, UART, I2S, I2C, PWM, or SPI.
- Experience managing a verification team.
- Strong knowledge of ASIC simulation tools and verification languages, including sign-off simulators and Verdi or Siloti.
- Fluency in verification languages such as UVM, OVM, SystemVerilog, Vera, or Verilog.
- Experience writing test plans and creating directed and random test cases.
- Strong scripting skills in Perl, Python, and Linux shells.
- Strong knowledge of Verilog, SystemVerilog, UVM, and C/C++.
- Experience using assertions, constrained random generation, and functional and code coverage.
- Knowledge of scripting languages such as Perl, Python, TCL, and Linux shells to automate verification methodologies and flows.
- Knowledge of digital design and two or three of AMBA AHB/AXI/APB-based SoC architecture, ADC/DAC, PCIe, Ethernet, CAN, or LPDDR interfaces.
- Analytical debugging and problem-solving skills, including quickly identifying and providing solutions under tight schedule pressure.
- Strong attention to detail.
- Good written and verbal communication skills.
- Good technical documentation skills.
- Good interpersonal skills and the ability to work independently and take initiative.
- Design, develop, and deploy UVM-based testbenches for multi-core, multi-threaded processor subsystems, emphasizing performance, power, and functional verification and sign-off for mixed-signal SoCs.
- Architect chip-level testbenches and verify SoCs and chipsets using ARM/RISC-V processor technology, AMBA AHB/AXI/APB, high-speed interfaces, peripheral interfaces, and mixed-signal AMS simulation environments.
- Lead SoC and mixed-signal verification teams and efforts.
- Build and manage the verification team and its tasks to meet tape-out schedules and production milestones.
- Develop and sign off on test plans and test cases.
- Develop testbenches for AMS and FC simulations.
- Develop tests to achieve more than 95% simulation coverage.
- Work with the design team to debug failures.
- Integrate and run BIST and DFT gate-level simulations.
- Measure code, line, toggle coverage, and other metrics.
- Run daily and weekly regressions and publish results.
- Own FC RTL and gate-level simulations.
- Mentor and lead a team of verification engineers.
- Work with systems and test engineering teams to help validate parts and release them to production.
About the company
Omni Design Technologies delivers high-performance, ultra-low power IP cores for mixed-signal SoCs that power devices across 5G, LiDAR, automotive networks, AI, image sensing, and IoT. It develops and validates IP blocks and licenses them to chip makers, offering customization and support to ensure seamless integration into customer designs. The cores are designed to work on FinFET processes down to 28nm, with proven silicon such as gigasample low-power ADCs and DACs on TSMC 28nm. The company differentiates itself through validated, silicon-proven IP, deep collaboration with customers and partners (e.g., LeddarTech, MegaChips), and a global design footprint (new Fort Collins design center). Its goal is to enable customers to build sophisticated, power-efficient, mixed-signal SoCs quickly by providing ready-to-license IP plus engineering services that fit their specific needs.
Company Size
51-200
Company Stage
Series A
Total Funding
$35M
Headquarters
Milpitas, California
Founded
2015
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Simplify's Take
What believers are saying
- September 17, 2025 Series A raised over $35 million from CDIB-TEN and others.
- February 6, 2026 CPO development positions Omni for AI data-center interconnect demand.
- 2026 hiring added Hinesh Shah, Poh Sim Gan, and expanded European recruiting.
What critics are saying
- Omni sells IP, so delayed customer tape-outs directly defer revenue recognition.
- Broadcom, Marvell, and Astera Labs compress pricing in optical I/O and data-converter IP.
- If 3nm CPO adoption stalls, Omni remains a niche licensing shop with limited scale.
What makes Omni Design Technologies unique
- Omni Design builds ultra-low-power analog IP for 3nm and 28nm nodes.
- Its 200G-class CPO AFE targets 224Gb/s PAM4 with integrated TX driver and TIA.
- The company spans data converters, optical I/O, radar, and 5G/6G connectivity.
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Benefits
- Company Equity
- Performance Bonus