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Astera Labs

Designs chips that connect data center systems

Principal Electrical Design Engineer

Board & Electronics DesignConfirmed live in the last 24 hours
Full-timeSan Jose, CA, USA$185k - $240kIn-person

About the Job

Requirements

  • A bachelor's or master's degree in Electrical Engineering or a closely related field is required.
  • At least 12 years of progressive hardware design experience, with deep expertise in board-level electrical engineering and demonstrated technical leadership across multiple product generations.
  • An extensive track record architecting and delivering production hardware at scale for server, networking, storage, or high-performance computing systems.
  • Expertise with high-speed SerDes-based systems supporting Ethernet, PCIe, or related protocols, including hands-on experience with PCIe Gen5/Gen6 and 400G/800G Ethernet system design.
  • Expert understanding of signal integrity fundamentals, including impedance control, differential-pair routing, channel-loss optimization, crosstalk mitigation, and layout review for high-speed interfaces.
  • Expert power-integrity and PDN design knowledge, including advanced sequencing, decoupling strategies, transient-response optimization, and system-level power-architecture tradeoffs.
  • Mastery of industry-standard schematic-capture and PCB design and review tools such as Cadence Allegro or OrCAD.
  • A proven track record leading hardware bring-up and debugging of complex platforms using oscilloscopes, protocol analyzers, and advanced laboratory instrumentation.
  • Demonstrated ability to lead cross-functional teams and influence technical direction across organizational boundaries, from architecture through validation and production.
  • A strong track record of mentoring engineers and elevating team capabilities.

Responsibilities

  • Define and own board-level hardware architecture and technical roadmaps across multiple product lines and platform generations.
  • Establish design standards, methodologies, and best practices that scale across the hardware engineering organization.
  • Drive architectural tradeoff decisions for complex multilayer PCBs integrating high-speed digital, analog, and mixed-signal circuitry, balancing performance, cost, schedule, and manufacturability.
  • Drive discussions on stack-up strategy, impedance optimization, and related signal-integrity development work.
  • Own power-delivery architecture strategy, including multirail regulation topologies, advanced sequencing schemes, transient-response optimization, protection philosophies, and power budgeting across platform generations.
  • Define and evolve hardware implementation strategies for management and control interfaces such as I2C, SPI, GPIO, and MDIO, as well as debug and observability architectures.
  • Own schematic capture and board-level design for complex multilayer PCBs with high-speed digital, analog, and mixed-signal circuitry.
  • Serve as the technical authority for board-level hardware development across high-performance server and connectivity platforms, including NIC cards, PCIe add-in cards, and chassis-integrated hardware.
  • Provide technical oversight and approval for schematic capture and board-level designs across multiple designs.
  • Lead component strategy and qualification roadmaps in partnership with suppliers, sourcing, and manufacturing teams.
  • Drive design-for-excellence initiatives, including design for test, design for manufacturability, and design for reliability, to improve manufacturability, yield, reliability, and production readiness across programs.
  • Define and own bring-up and validation strategy for new hardware platforms, establishing frameworks that improve first-pass success rates across the organization.
  • Lead root-cause analysis of complex and escalated hardware issues across high-speed interfaces, power delivery, clocks, resets, and control paths.
  • Drive systemic improvements to debug methodologies, validation coverage, and failure-analysis processes.
  • Partner with firmware, software, and system teams to define and validate initialization sequences, telemetry, diagnostics, and platform-level functionality.
  • Own corrective-action frameworks and feed lessons learned into design standards and review processes.
  • Serve as the technical point of escalation and decision-maker for hardware design challenges across the organization.
  • Work with signal-integrity/power-integrity, mechanical, thermal, firmware, system, and manufacturing teams throughout the product lifecycle, driving alignment and resolving cross-domain technical conflicts.
  • Interface with silicon vendors and internal ASIC teams on platform architecture, bring-up, errata resolution, compliance, and next-generation readiness.
  • Mentor and develop senior and lead engineers, raising the technical bar across the hardware engineering team.
  • Lead and contribute to design reviews, architectural reviews, and technical publications that advance the team's collective expertise.
  • Represent the hardware engineering organization in executive reviews, customer engagements, and industry forums as needed.

Desired Qualifications

  • Experience defining architecture for NIC cards, accelerator cards, or other PCIe add-in-card platforms across multiple generations.
  • Experience leading server chassis or system-board design programs in dense, thermally constrained, high-availability environments.
  • Deep expertise with 800G Ethernet and emerging 1.6T electrical interfaces and system-integration challenges.
  • Experience architecting solutions using retimers, redrivers, advanced clocking architectures, and high-speed interconnect subsystems.
  • Expertise in compliance and validation workflows for PCIe and Ethernet platforms, including contributions to industry specifications or standards bodies.
  • Experience driving contract-manufacturer relationships, production-ramp strategies, and yield optimization for complex hardware products.
  • Scripting and automation proficiency in Python or similar languages for laboratory automation, measurement analysis, hardware-characterization workflows, and design-flow optimization.
  • Experience influencing product-strategy and roadmap decisions at the organizational level.
  • An advanced degree is preferred.

About the Company

Astera Labs

Designs chips that connect data center systems

Astera Labs designs chips and hardware modules that move data between processors, memory and accelerators in data centers. Its customers include cloud providers, chip vendors and equipment makers building servers and large computing clusters for AI and other workloads. Retimers restore signal quality, switches connect devices and memory controllers expand the memory available to computing systems, while COSMOS software monitors and manages these links. The company sells its products directly and through distributors, using outside manufacturers to fabricate and assemble its hardware. Astera Labs was founded in 2017 and is headquartered in San Jose, California.

Company size
501-1,000
Company stage
IPO
Headquarters
San Jose, CA
Founded
2017

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