Principal Engineer - Physical Design
About the job
- A Bachelor of Engineering/Bachelor of Technology or Master of Engineering/Master of Technology degree and at least 15 years of experience on high-complexity SoC designs, including at least one SoC at 7 nm or lower.
- Demonstrate knowledge and implementation strategies for creating an IO ring in accordance with design specifications.
- Have deep knowledge of ESD, latch-up, and other foundry requirements, as well as placement strategies.
- Have hierarchical design implementation knowledge, including partitions, HMs, and tiles pushed down to each core or tile.
- Understand feed-through planning and implementation.
- Understand PG creation and push-down methodologies.
- Understand analog components and their placement requirements according to design specifications.
- Demonstrate RDL knowledge and experience working with packaging for SoC floorplan design.
- Conduct physical verification clean-up on floorplans and ensure self-derivation in all sign-offs, including Physical Verification, ESD, and foundry/analog requirements.
- Have working knowledge of place-and-route implementation, physical verification, and static timing analysis.
- Have experience with SoC RTL-to-GDSII implementation, including top-level clocking strategy and implementation.
- Own P&R flow, including scripting and flow deployment for SoCs and blocks.
- Perform hands-on SoC/full-chip floorplanning, integration, and place-and-route, along with P&R flow development.
- Establish die integration plans that optimize for package and board constraints.
- Perform bump planning and die file generation, and close the loop with the package team on signal and power bump placement restrictions.
- Create physical databases for IP or SoCs and collaborate with architects to optimize IP placement for latency, die area, and aspect ratio.
- Collaborate with design teams on clocking and dataflow to deliver physical block-level floorplans for APR.
- Derive specifications and collaterals for IP blocks to execute floorplanning and automatic place-and-route at subsequent hierarchies.
- Coordinate with the power delivery team on trade-offs for metal allocation between signal and power.
- Maximize die-per-reticle and good-die-per-wafer, and select technology to maximize metal-layer usage.
- Integrate all dies in a package and complete relevant checks before tape-out.
- Supervise, lead, and mentor junior team members.
- Have in-depth knowledge of Physical Verification tools such as Synopsys ICV and Calibre Physical Verification Tools.
- Know package physical-verification checks, IO/bump physical-verification clean-up, and physical-verification rules such as antenna, density, DFM, DFY, and DPT at technology nodes of 7 nm or less.
- Have led physical-verification activities on SoC designs, with expertise in DRC, LVS, DFM, HV checks, and clean-up.
- Have expertise in running physical-verification checks on flat or hierarchical SoC designs with multiple power domains.
About the company
SiMa.ai provides a no-code, drag-and-drop environment for building, training, and deploying machine learning models on edge devices. Its platform lets users visually assemble ML solutions without writing code, and runs on its own MLSoC silicon designed for edge computing to reduce latency and speed up inference close to data sources. The product works by combining the no-code development tools with specialized edge-ready hardware, enabling deployment of ML applications such as computer vision on edge devices. SiMa.ai differentiates itself from competitors by pairing a purpose-built MLSoC with an integrated no-code development platform, plus an ecosystem of a developer portal, expert consulting, and a partner program to accelerate AI innovations at the edge. The company aims to broaden access to edge ML, helping individuals and organizations deploy efficient AI at the edge across various industries.
Company Size
201-500
Company Stage
Series C
Total Funding
$495M
Headquarters
San Jose, California
Founded
2018
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Simplify's Take
What believers are saying
- Oct. 2026 workshops in Burlington, Austin, and Bloomington deepen developer adoption.
- SiMa.ai says revenue quadrupled from 2024 to 2025 and momentum continued in 2026.
- Customer list includes Bosch, Emerson, Synopsys, Micron, Intrinsic, and TRUMPF SE.
What critics are saying
- Nvidia Jetson Thor already anchors humanoids; SiMa.ai must displace entrenched design wins by 2028.
- Gen 3 hardware slips to H1 2028, leaving years for competitors to widen benchmarks.
- If Palette Neat or Modalix miss production economics, SiMa.ai becomes a niche prototyping vendor.
What makes SiMa.ai unique
- Sep. 2026 Series C: $500 million raised, $1.45 billion valuation, signaling investor conviction.
- Modalix is in production now, with Palette Neat and pin-compatible SiMa SoM.
- SiMa.ai targets robots, drones, and ADAS with sub-10W to 60W edge inference.
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Benefits
- Company Equity