C

ChipAgents

Agentic AI platform automates RTL design

Research Scientist

Full-Time
$150k - $350k/yr+ Equity
Mid
Bachelor's
San Jose, CA, USA+1 moreMore locations: Santa Barbara, CA, USA
In Person
AI & Machine LearningAI Research

About the job

Requirements
  • A degree in Computer Science, Machine Learning, Electrical Engineering, or a related field, or equivalent research experience.
  • A strong background in large language models, deep learning, and modern machine learning frameworks such as PyTorch and JAX.
  • Experience with artificial intelligence agent architectures, autonomous systems, or multi-agent workflows.
  • Strong programming skills in Python and experience with large-scale model training infrastructure.
  • The ability to balance research rigor with pragmatic engineering to deliver real-world impact.
Responsibilities
  • Conduct research in artificial intelligence-assisted electronic design automation, focusing on practical solutions that accelerate chip design and verification workflows.
  • Train and deploy large language models using substantial compute resources, optimizing for performance and real-world applicability.
  • Design, build, and benchmark agentic artificial intelligence systems using state-of-the-art large language models and proprietary in-house models.
  • Translate research innovations into production-ready features that integrate into hardware engineering workflows.
  • Collaborate with cross-functional teams to identify high-impact research directions based on customer needs and field deployment learnings.
  • Publish findings and contribute to the broader artificial intelligence and electronic design automation research communities where appropriate.
Desired Qualifications
  • Familiarity with electronic design automation tools, register-transfer-level design, or hardware-software co-design.

About the company

ChipAgents provides an agentic AI platform embedded in code editors to automate RTL design, debugging, and verification for semiconductors. It uses AI agents to generate RTL specifications from natural language, autocomplete Verilog, create testbenches, and autonomously verify code through simulations. The platform integrates with existing EDA workflows and targets hardware engineers to boost productivity, with early traction from 80 leading semiconductor companies. The goal is to shorten pre-silicon design cycles from weeks to days by automating repetitive tasks and enabling language-driven design and testing.

Company Size

11-50

Company Stage

Series A

Total Funding

$134.1M

Headquarters

San Jose, California

Founded

2024

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Simplify's Take

What believers are saying

  • ChipAgents said July 29, 2026, it deployed across 120 semiconductor companies and grew ARR 6x.
  • Andes Technology cut a verification workflow from months to three weeks using ChipAgents in 2026.
  • NVIDIA expanded its July 26, 2026 collaboration, reinforcing ChipAgents’ technical moat and distribution.

What critics are saying

  • Synopsys, Cadence, and Siemens EDA can bundle rival agents into existing design flows by 2027.
  • Micron and MediaTek are both investors and customers, creating concentration risk if deployments stall.
  • Autonomous chip-design agents face silicon-signoff liability; one bad bug can kill enterprise trust immediately.

What makes ChipAgents unique

  • ChipAgents targets RTL, verification, and debug, not generic coding assistants, as of 2026.
  • Renoir combines domain-specialized models with agent workflows across specs, waveforms, and EDA outputs.
  • William Wang’s UCSB lab roots and veteran advisors from Synopsys, Cadence, and Siemens sharpen domain credibility.

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Benefits

  • Unlimited Paid Time Off
  • Health Insurance
  • Dental Insurance
  • Vision Insurance
  • 401(k) Retirement Plan
  • 401(k) Company Match
  • Paid Vacation
  • Company Equity

Growth & Insights and Company News

6 month growth

0%

1 year growth

20%

2 year growth

33%
HPCwire
Oct 27th, 2026
ChipAgents expands full-stack agentic AI across digital and analog chip design.

ChipAgents expands full-stack agentic AI across digital and analog chip design. October 27, 2026 Press play to listen to this content Powered by the IC-star engine, the ChipAgents platform connects organizational design knowledge, self-improving agentic workflows and physics-aware intelligence to autonomously move engineering intent toward verified outcomes SANTA CLARA, Calif., Oct. 27, 2026 - ChipAgents has announced the expansion of its AI-native engineering platform across digital and analog chip design, bringing more of the semiconductor development flow onto a shared agentic foundation. AI models are evolving on a months-long cadence, while traditional chip development can take 12-18 months or longer. Building the next generation of custom silicon for AI requires engineering teams to move faster across increasingly complex digital and analog design cycles. Yet much of that work still happens across fragmented tools, teams and workflows, forcing engineers to manually carry context from one stage of the design process to the next. ChipAgents' full-stack approach enables engineers to define objectives, constraints and critical judgment calls while AI agents carry more of the execution forward, reasoning over design context, operating engineering tools, evaluating results and determining the next action toward closure. "Autonomous semiconductor engineering is a systems problem," said William Wang, founder and CEO of ChipAgents. "It is not enough to make an individual model stronger or add more agents to a workflow. The AI needs to understand the organization's design knowledge, coordinate the right models and tools, evaluate real engineering results and account for the physical consequences of each decision. We built ChipAgents around that entire system so engineers can focus on the design objective while AI handles more of the execution underneath." Powering the platform is IC-star, ChipAgents' chip neural engine for digital and analog semiconductor engineering. IC-star is designed to navigate the enormous semiconductor design space by evaluating the current design state and determining the next best action rather than requiring engineers to manually decide which model, tool or workflow to run next. IC-star brings together four tightly integrated capabilities: * IC Design Ontology: A persistent context layer for engineers and agents that unifies design knowledge, plans, reusable skills and customer-specific methodologies, continuously improving the system through engineering feedback. * Reasoning Core: Plans and coordinates agents, models and engineering tools around an objective to execute long-horizon workflows such as root-cause analysis, PPA-aware RTL closure and analog layout generation. * Multiphysics-Aware Models: Predict timing, PPA, DRC, DFT and analog physical design to enable multi-objective co-optimization at generation time. Renoir, ChipAgents' semiconductor-specific, physics-aware LLM, serves as a core domain model within this layer. * Design-Driven Model Navigator: Dynamically routes work across AI models based on the task, balancing quality of results, time to results and cost. Together, those capabilities allow ChipAgents to co-optimize model choice, token consumption, tool execution, engineering review and physical feedback around the total engineering outcome, rather than optimizing each AI task independently. ChipAgents measures value in the time it takes for designs to converge, engineering effort and overall execution costs across both digital and analog chip design. The same foundation spans both digital and analog engineering. Digital workflows supported by ChipAgents include specification analysis, architecture exploration, RTL design, functional and formal verification, root-cause analysis and debug, coverage closure and PPA-aware optimization. Analog workflows extend across topology and schematic design, simulation, behavioral modeling, layout generation and physical verification. ChipAgents is expanding its collaboration with NVIDIA to fine-tune Nemotron models for AI-native digital and analog design workflows. ChipAgents reports initial results show that the post-trained Nemotron model achieves performance competitive with frontier models, including Fable 5.1 and GPT-6 Astra, based on open benchmarks, while delivering the highest performance and best cost efficiency among the open-weight models evaluated. These results mark a meaningful step toward AI that can carry engineering intent from specification through physical implementation, making autonomous chip design more reliable and practical for engineering teams. "For Ambiq, advancing ultra-low-power design means optimizing power, performance, and area together. ChipAgents' IC-star brings multi-objective optimization to our digital design workflows, helping us accelerate RTL development, test case generation, and root cause analysis," said Scott Hanson, founder and CTO of Ambiq. "Security is a fundamental requirement for us, and ChipAgents' focus on protecting sensitive data and IP is essential to enabling AI-native flows in our engineering environment." Analog design presents a particularly challenging environment for AI because engineering decisions depend on circuit behavior, waveforms and physical tradeoffs that cannot be captured through code generation alone. By connecting agentic execution with design context and physics-aware models, ChipAgents can create dynamically programmable autonomous workflows in which AI generates, simulates, evaluates and iterates while engineers retain control over requirements and signoff. "IC design demands deep engineering expertise and meticulous attention to detail. Over the past year, we have worked with ChipAgents to bring AI into our development workflows, creating a foundation that blends engineering knowledge with AI-powered assistance across the IC design lifecycle," said Dave Brownell, vice president of engineering enablement at Analog Devices. "We see tremendous potential to build on this foundation, helping our teams accelerate development and focus more of their expertise on delivering innovative, high-performance products." "We are adopting ChipAgents to accelerate our chip and IP design and verification workflows," said Simon Blake-Wilson, senior vice president and general manager of silicon IP at Rambus. "By combining Rambus' deep semiconductor and silicon IP expertise with ChipAgents' IC-star engine, we see an opportunity to help our customers bring advanced chips to market faster and achieve better design outcomes within their preferred design environments." "The opportunity for agentic AI is to turn a chip team's accumulated design knowledge into the ability to explore more ideas, learn from simulation and resolve engineering tradeoffs faster," said Tim Costa, vice president and general manager of industrial and computational engineering at NVIDIA. "Pairing specialized NVIDIA Nemotron models with ChipAgents' physics-aware workflows can shift the engineer's role from managing each tool run to directing a design strategy, with agents translating simulation and verification feedback into the next design decision." The expanded platform builds on more than 200 semiconductor enterprise deployments across a growing range of design and verification workflows. Recent deployments illustrate the measurable impact of moving AI deeper into semiconductor engineering. Andes Technology reduced one processor-verification workflow from two to three months to approximately three weeks and shortened a processor customization project by 30%. eMemory reduced engineering effort for datasheet analysis and verification-testbench construction by approximately 80%. Whalechip reduced semiconductor root-cause analysis from days to approximately 15-60 minutes per round while identifying four critical bugs. ChipAgents integrates securely with customers' existing tools and workflows, whether deployed on-premises or in the cloud. The architecture preserves organizational knowledge and supports on-premises self-improvement for organizations requiring greater control over proprietary design data. ChipAgents will provide a deeper technical look at the IC-star engine and its application across digital and analog design during an Oct. 29 webinar. About ChipAgents ChipAgents is a leading agentic AI platform for semiconductor engineering, providing end-to-end automation for complex digital and analog chip design, verification and debugging workflows. The platform combines semiconductor-specific intelligence, autonomous agents and AI-native tools to accelerate chip development and improve productivity. Founded in 2024, ChipAgents serves semiconductor companies worldwide and is headquartered in Santa Clara, California. For more information, visit chipagents.ai. CERN, the world's largest particle physics laboratory, has spent decades collecting enormous amounts of data... Nvidia says it can cut the time to set up an AI data center from... Europe is making progress with its AI for science initiative, dubbed Resource for AI Science... Nvidia has announced the general availability of cuDSS, a software library designed to speed up... Nvidia made a slew of announcements at GTC Berlin today that demonstrate its commitment to... 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StreetInsider
Oct 22nd, 2026
Rambus invests in ChipAgents and deploys its agentic AI chip design platform

Rambus has invested in ChipAgents and will use its agentic AI platform across its chip and silicon IP design and verification work. The companies announced a strategic partnership to bring agentic AI into chip design. Financial terms were not disclosed. The two will also offer combined capabilities to customers in their preferred design environments. ChipAgents, founded in 2024 and based in Santa Clara, California, converts specifications and code into production-ready design assets. "By adopting the ChipAgents platform, we see opportunities to accelerate the pace of chip and IP development, enhance engineering productivity, and strengthen our long-term position in AI and data-center infrastructure," said Luc Seraphin, president and chief executive officer of Rambus.

EE Times Asia
Oct 15th, 2026
SEMICON west 2026: NVIDIA expands GPU libraries for AI-driven semiconductor manufacturing.

SEMICON west 2026: NVIDIA expands GPU libraries for AI-driven semiconductor manufacturing. Article by: NVIDIA. NVIDIA and industry partners are applying accelerated computing and AI agents to chip simulation, process optimization, inspection and fab automation. NVIDIA has expanded its CUDA-X software portfolio to support AI-driven semiconductor design and manufacturing, with chipmakers and equipment suppliers adopting GPU-accelerated libraries for simulation, inspection and process optimization. The portfolio includes the new cuPotential library, which accelerates simulations of atomic and molecular interactions. NVIDIA said the tools will help engineers model materials, analyze inspection data and evaluate manufacturing changes before applying them to production. "The semiconductor industry made the AI revolution possible. Now, AI is transforming how chips are built," said Tim Costa, vice president and general manager of industrial and computational engineering at NVIDIA. "As fabs race to meet demand for advanced chips, NVIDIA CUDA-X and Omniverse libraries give AI agents accelerated simulation and inspection tools to help engineers manage complexity, improve yield and advance AI-defined fabs." CUDA-X targets semiconductor simulation The new cuPotential library provides GPU-accelerated functions for modeling electrical forces and other interactions among atoms. NVIDIA said early-access testing showed an additional 2-3x acceleration over existing GPU-optimized workflows. Synopsys is among the early adopters. Other CUDA-X libraries target different engineering workloads. cuEST models electronic behavior, while cuDSS accelerates complex engineering simulations. Synopsys is using the three libraries for semiconductor simulation. Early results showed a potential 30x speedup in QuantumATK using cuEST and a 12x speedup in S-Device using cuDSS. Its AgentEngineer solutions also work with NVIDIA Nemotron models and NeMo software to support AI agents for chip design and verification. Cadence is applying NVIDIA accelerated computing and AI models to electromechanical design, including semiconductor packaging and printed circuit boards. Its AuraStack AI Super Agent has optimized advanced packages for thermal and mechanical stress analysis up to eight times faster using cuDSS with Cadence Celsius. COMSOL is using cuDSS to accelerate multiphysics simulations for semiconductor equipment and process development, reporting up to 10x faster simulations. An upcoming COMSOL MCP Server will use NVIDIA's Nemotron Ultra model for AI-assisted modeling and design exploration. Voltai's Voltaire platform combines AI agents with GPU-accelerated solvers for 3D integrated-circuit design. The company said its approach can reduce electrothermal-mechanical simulation workflows from months to a day. ChipAgents is developing specialized AI models for chip design and working with NVIDIA on Build-A-Chip Bench, a benchmark for evaluating AI agents across workflows from specifications to graphic data system (GDS) output. Libraries support process modeling and lithography NVIDIA is also targeting manufacturing preparation and optimization. Its cuLitho library accelerates computational lithography, while NanoVDB supports processing of three-dimensional data and PhysicsNeMo provides a framework for training physics-based AI models. Siemens is using cuLitho to accelerate chip-pattern refinement and photomask preparation in its Calibre software. Its Solido team is also developing AI-driven characterization workflows using Nemotron models and NeMo libraries. Lam Research plans to integrate NanoVDB into SEMulator3D, its semiconductor process modeling platform. The company expects the addition to accelerate selected wafer-etch modeling workloads by up to 30x. Lam has also demonstrated PhysicsNeMo applications that reduce plasma-prediction simulation times from days to milliseconds. Luminary is using PhysicsNeMo to train models that predict temperature, pressure drop and thermal stress in semiconductor packages. The company said this approach allows engineers to explore 100 times more design configurations within the same schedule without running a separate simulation for each option. AI accelerates inspection and test For inspection and test, NVIDIA is promoting its NPP image-processing library and RAPIDS cuDF for GPU-accelerated data processing. Research institute imec is using NVIDIA computing to reduce noise in scanning electron microscope images for sub-nanometer chip measurements. It is also applying cuLitho to computationally intensive optical proximity correction, reporting a 30% improvement in the lithography process window. KLA has developed an NPP normalized cross-correlation kernel based on insights from its production software. The company reported performance up to 50 times faster than earlier CPU implementations, comparable with its hand-optimized versions. Teradyne is using NPP, RAPIDS cuDF and CuPy to accelerate test and maintenance workflows. The company reported approximately 85x faster probe-maintenance inference, which can help identify degrading probes before they affect yield. Advantest has integrated NVIDIA Nemotron and Kumo-Anomaly into its ACS RTDI platform for semiconductor production analytics. The system uses Grace Blackwell computing for real-time diagnostics and recommendations for corrective action in test cells. Advantest is also applying NeMo Switchyard AI agents to automate model selection and shorten test-workflow response times from hours to minutes. Digital twins extend AI into fab operations NVIDIA's technologies also support factory simulation and automation, where equipment data and digital models can help engineers evaluate process changes and production layouts. Applied Materials is using NVIDIA Omniverse and CUDA-X libraries, including cuDSS, cuEST and PhysicsNeMo, for materials discovery, process development and fab optimization. The company reported up to 35x faster chamber simulations and is developing fab digital twins to optimize layouts and material flow. Analog Devices is combining Synopsys physics simulation with NVIDIA Isaac Sim and Omniverse libraries to model sensor behavior in robotic systems. FANUC and Foxconn are connecting robot models to NVIDIA's Mega Omniverse Blueprint, allowing manufacturers to simulate and validate robotic operations in factory digital twins before deployment. OMRON is using NVIDIA Cosmos world models and the Metropolis Blueprint for video search and summarization in inspection equipment. Its work focuses on AI agents that combine visual data, equipment documentation and manufacturing knowledge to help engineers investigate printed circuit board defects and support troubleshooting and quality control.

MarketScreener
Oct 14th, 2026
ChipAgents collaborates with NVIDIA to launch Build-A-Chip-Bench for autonomous chip design and implementation.

ChipAgents collaborates with NVIDIA to launch Build-A-Chip-Bench for autonomous chip design and implementation. Published on 10/14/2026 at 02:50 pm EDT S&P Capital IQ ChipAgents introduced Build-A-Chip-Bench, a benchmark built in collaboration with NVIDIA designed to test whether AI agents can carry an end-to-end digital chip-design task from specification through physical implementation and verified GDS; thus, measuring true progress toward semiconductor design superintelligence. ChipAgents developed Build-A-Chip-Bench with NVIDIA to evaluate AI agents across the end-to-end digital IC design flow, from specification through physical implementation and verified Graphic Design System (GDS). Unlike point benchmarks focused primarily on RTL generation or verification, Build-A-Chip-Bench tests whether agents can meet functional, timing, power, area, and physical-verification requirements together. Build-A-Chip-Bench extends evaluation across the complete chip design flow, including architecture, microarchitecture, RTL, functional verification, logic synthesis, floor planning, placement, clock-tree synthesis, routing, timing and power signoff, and physical verification. Initial evaluations found that tested agents passed functional verification on ~40% of tasks on average, while only approximately 10% met the required physical performance, power and area (PPA) targets. The results illustrate an important distinction in AI-driven semiconductor design: generating functionally correct RTL is only one part of the engineering challenge. These results highlight the challenge of carrying functionally correct designs through physical implementation under the benchmark?s test conditions. Autonomous systems must also reason across abstraction levels, preserve validated behavior through revisions, operate specialized engineering tools and plan around expensive real-world physical feedback. Build-A-Chip-Bench is a benchmark developed by ChipAgents with technical expertise from NVIDIA on the benchmark suite and scoring rubric. It measures both functional correctness and the ability to meet downstream physical-design constraints. (C) S&P Capital IQ - 2026

Yahoo Finance
Oct 14th, 2026
ChipAgents and NVIDIA launch chip design benchmark: AI agents pass 40% of tests, only 10% hit PPA targets

ChipAgents, a Santa Clara startup building AI agents for semiconductor engineering, has launched Build-A-Chip-Bench with NVIDIA. The benchmark tests whether AI agents can take a digital chip design from specification through physical implementation and verified Graphic Design System (GDS) output. Existing tests largely stop at generating register-transfer level (RTL) code or verifying it. The new benchmark covers the full flow, and agents must meet functional, timing, power, area, and physical-verification requirements together. Initial results show a wide gap. Tested agents passed functional verification on about 40% of tasks, but only about 10% met physical performance, power and area targets. "The real challenge is carrying engineering intent through a long sequence of interconnected decisions," said William Wang, ChipAgents' founder and chief executive officer.