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Renesas Electronics

Automotive-focused MCUs, SoCs, analog devices

Staff Engineer - Physical Design

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeBengaluru, Karnataka, IndiaNo salary listedHybrid

About the Job

Requirements

  • A B.Tech or M.Tech in Electrical Engineering.
  • At least 7 years of experience in physical design, focusing on subsystem-level closure for complex hierarchical SoCs at advanced nodes (7nm, 5nm, or below).
  • Strong expertise in timing closure, congestion management, and physical implementation at the block and subsystem level.
  • A solid understanding of SoC-level floorplanning and clocking methodologies, including clock domain partitioning, clock tree architecture, skew management, and clock gating, and the ability to collaborate effectively on SoC-level activities without leading them.
  • Hands-on experience with industry-standard physical design and timing tools such as Synopsys ICC2, Cadence Innovus, PrimeTime, and signoff platforms.
  • Proficiency in scripting and automation with Tcl, Python, and Perl to support closure flows and methodology development.
  • Deep knowledge of SoC design flows and the ability to work closely with timing closure, power integrity, clocking, and verification teams.
  • A solid understanding of low-power design techniques and power-aware physical implementation.

Responsibilities

  • Lead MCU, subsystem, and block-level closure efforts, focusing on timing closure, congestion resolution, power integrity, and physical implementation.
  • Collaborate with SoC-level teams to align clocking and floorplanning strategies, leveraging strong understanding of SoC methodologies without direct ownership of SoC-level activities.
  • Work on different power domains and implement UPF.
  • Apply knowledge of clocking methodologies to ensure subsystem clock domain integration aligns with the overall SoC clock architecture.
  • Develop and refine subsystem closure methodologies and automation flows to improve design quality and efficiency.
  • Mentor and guide physical design engineers within subsystem teams, promoting best practices and methodology adoption.
  • Work cross-functionally with RTL designers, STA, power, verification, and backend teams to ensure smooth subsystem integration and closure.
  • Proactively identify and mitigate physical design risks, coordinating with SoC teams on potential impacts and solutions.

About the Company

Renesas Electronics

Automotive-focused MCUs, SoCs, analog devices

Renesas manufactures and sells MCUs, SoCs, and analog/power semiconductor devices to OEMs, focusing on automotive, industrial, infrastructure, and IoT markets. Its chips are building blocks that run embedded software and manage power and signals, and its Winning Combinations offer pre-tested system architectures to speed up design. It differentiates itself by growing through acquisitions to offer a broad, integrated portfolio and by moving toward a unified digital design platform to reduce integration work. Its goal is to become a leading supplier of these components and provide a single platform for electronics design that speeds time-to-market.

Company size
10,001+
Company stage
IPO
Headquarters
Tokyo, Japan
Founded
2002

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