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Architect Labs

AI-driven automated ASIC chip design platform

Member of Technical Staff - AI for Chip Design

AI Application EngineeringConfirmed live in the last 24 hours
Full-timePalo Alto, CA, USAIn-person

About the Job

Requirements

  • An MS or PhD in Electrical Engineering, Computer Engineering, EECS, or a closely related field.
  • Strong industry or research experience as an RTL design or Design Verification engineer, with a solid understanding of the modern chip design flow end to end.
  • Excellent software engineering fundamentals, including the ability to write clean, production-grade Python or TypeScript, build tooling, and work in modern engineering environments.
  • Demonstrated ability to own ambiguous problems end to end, prototype quickly, and productionize what works.
  • Genuine excitement about applying frontier AI to hardware; prior applied-AI or ML research experience is not required.

Responsibilities

  • Design and build AI agents that tackle core chip-design tasks, grounding model behavior in how real hardware engineers work.
  • Own end-to-end agent workflows, including scaffolding, tool use, evaluation harnesses, and domain-specific infrastructure that makes agents useful on actual design problems.
  • Curate high-quality data, define evaluation criteria, and encode the engineering judgment needed to distinguish plausible outputs from correct ones.
  • Partner with ML research, post-training, and infrastructure teams to translate hardware domain expertise into reward signals, benchmarks, and training signals.
  • Prototype, dogfood, test, and iterate quickly, translating ambiguous chip-design challenges into concrete agent capabilities that ship.

Desired Qualifications

  • Prior experience on AI-for-chip-design or AI4EDA efforts at Google, NVIDIA, or chip or EDA companies.
  • Experience building, using, or evaluating LLM-based tooling for engineering workflows.
  • Publications or open-source contributions at the intersection of ML and EDA, including DAC, ICCAD, DVCon, MLCAD, NeurIPS, ICLR, or ICML.
  • Experience as an early engineer at a deeptech or AI startup.

About the Company

Architect Labs

AI-driven automated ASIC chip design platform

Architect Labs develops AI-powered tools to automate and speed up ASIC design for the semiconductor industry. It combines artificial intelligence with an integrated workflow for hardware exploration, SystemVerilog construction, verification, and physical design to produce end-to-end, verified chip designs. The platform aims to discover new architectures and generate ready-to-tute designs that are validated for modern machine learning workloads, enabling hardware/material co-optimization between AI models and specialized silicon. Compared to traditional EDA and ASIC design services, Architect Labs focuses on AI-guided architecture search, automated verification, and full-stack co-design to reduce time, cost, and labor in chip development. The goal is to shorten multi-year design timelines, lower upfront costs, and empower more specialized, high-performance silicon for data centers, automotive, robotics, and edge applications.

Company size
11-50
Company stage
Seed
Total funding
$24M
Headquarters
Palo Alto, CA
Founded
2025

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