Senior Staff Physical Design Timing Engineer - Static Timing Analysis

About this role

We are hiring a Physical Design Timing Engineer to help drive backend digital execution for some of the leading photonics based interconnect solutions. You will work alongside a team of world-class scientists and engineers in defining how the system will be optimized and trailblaze problems that are new to the industry. If your passion is innovation, solving challenging technical problems and doing impactful work you should join our team.

In this job you will be responsible for timing constraints development, STA and timing closure on  leading edge CMOS technologies and flows. This includes synthesis through place and route, timing closure, and tapeout signoff.

Responsibilities

• Drive the STA sign-off  for our flagship Silicon photonics chips at various technology nodes. 
• Analyze fab guidelines and work with the methodology team to incorporate sign off corners, margins, and derates into timing analysis flows and methodologies.
• Collaborate with the  architecture, RTL, and DFT teams to analyze the timing complexities and develop consolidated timing modes and constraints for synthesis, along with PnR and chip timing sign-off flows.
• Analyze and understand the tradeoffs between power/performance and area goals to drive them into overall chip implementation flows.
• Run full-chip STA and accurately project the timing summary across scenarios.
• Leverage Tempus/PrimeTime to automate timing ECO generation for effective closure and support physical design implementation.
• Document best practices and lessons learned to drive continuous improvements in future projects.

Qualifications:

• Bachelor’s degree in Electrical Engineering or Computer engineering
• 12 years of Physical Design experience, with a minimum of 5 years hands-on experience in ASIC STA and timing constraints development, timing closure with Cadence or Synopsys tools 
• Experience in driving timing closure by effectively managing on-chip variation derates, optimizing multi-mode multi-corner constraints, and implementing robust clock tree building strategies
• Well versed with scripting languages like TCL and Python, PERL, or Shell
• Strong problem solving skills with attention to every technical aspect
• Be a strong team player with clear and precise communication skills

Preferred Qualifications:

• Master’s degree in Electrical Engineering or Computer engineering
• A minimum of 8 years of hands-on experience in ASIC STA and timing constraints development, timing closure with Cadence or Synopsys tools 

Salary Range: total compensation goes beyond base salary, it also includes a new hire equity grant, annual performance-based equity, and other rewards that recognize your impact and contribution. 217000 - 267000 USD