Firmware Intern

Google partners with Marvell on new AI chips to challenge Nvidia. The partnership. Alphabet Inc.'s Google is currently in talks with Marvell Technology to develop two new chips aimed at running AI models more efficiently. This collaboration, reported by The Information on Sunday citing two people with knowledge of the discussions, marks a strategic shift in how the tech giant approaches its hardware infrastructure. Google has long relied on internal custom silicon, but external partnerships are becoming increasingly common as the demand for AI compute scales beyond what internal labs can easily manage. The partnership is not merely about securing manufacturing capacity. It is a direct effort to improve performance metrics that define the modern AI landscape. Efficiency is the metric that matters now. Training and inference models consume massive amounts of power and memory bandwidth. By integrating Marvell's expertise, Google aims to address these bottlenecks before they become critical failures in production environments. The companies aim to finalize the design of the memory processing unit as soon as next year before handing it off for test production. While Reuters could not immediately verify the report, the context suggests a necessary evolution. Google faces a crowded market where hardware compatibility often dictates software deployment. If Google's Tensor Processing Units (TPUs) remain proprietary, adoption is limited to Google Cloud customers. If these new chips can run on broader hardware stacks, they could expand the addressable market for Google's infrastructure services. The report indicates the companies are focused on efficiency. In high-compute environments, efficiency directly translates to cost savings. For cloud providers, every watt of power consumed during inference reduces the margin available for growth. Hardware strategy. One chip is a memory processing unit designed to work with Google's tensor processing unit (TPU), and the other chip is a new TPU built specifically for running AI models. This distinction is vital for understanding Google's hardware roadmap. The memory processing unit addresses a specific weakness in current architectures. AI models often starve for data movement rather than raw compute power. Memory bandwidth is the primary constraint in modern large language model inference. The second chip, a new TPU, represents a direct competitor to Nvidia's dominant GPUs. Nvidia currently controls the vast majority of the market for AI training and inference. Google has been pushing to make its TPUs a viable alternative to Nvidia's GPUs. This is not a secondary goal. TPU sales have become a key driver of growth in Google's cloud revenue. The company needs to diversify its revenue streams beyond general-purpose computing. The architecture of these new chips matters. Nvidia's GPUs rely on CUDA, a proprietary software stack that developers have built over decades. Google's TPUs rely on JAX and other frameworks. By developing a new TPU specifically for running AI models, Google is attempting to bridge the gap between software frameworks and hardware acceleration. If the new TPU can match Nvidia's performance-per-watt while running on a compatible software stack, it could disrupt the current ecosystem. However, the strategy requires balancing performance with compatibility. Developers prefer hardware that supports their existing workflows. If the new TPU requires significant code rewriting, adoption will be slow. The memory processing unit helps here by optimizing data transfer between the memory and the compute core. This reduces latency without increasing clock speeds. In practical terms, this means faster model loading times and reduced inference costs for enterprise customers. The financial stakes are high. Nvidia's dominance is built on a moat of software and hardware integration. Google cannot simply match Nvidia's raw compute power. It must offer better economics. The new chips aim to run AI models more efficiently. Efficiency implies lower operating costs for data centers. For Google, this means higher margins on cloud infrastructure sales. For customers, it means lower bills for running large language models. Financial goals. TPU sales have become a key driver of growth in Google's cloud revenue as the company aims to show investors that its AI investments are generating returns. This is the primary motivation behind the partnership. Investors scrutinize capital expenditure on hardware. If Google spends billions on custom silicon but cannot sell the hardware effectively, returns on investment suffer. The new partnership with Marvell provides a pathway to externalize these assets. Google's internal TPU usage is well documented. It powers the search engine and the recommendation systems that drive ad revenue. Now, the goal is to monetize that silicon outside of Google Cloud's internal use. Selling TPUs to third-party enterprises is difficult. Most enterprises rely on Nvidia GPUs because the software ecosystem is mature. Google needs to change that perception. The new TPU built specifically for running AI models is designed to compete with Nvidia's dominant GPUs. Competition forces innovation. If Google can offer a product that is cheaper or faster than Nvidia's offering, it will capture market share. This is not about beating Nvidia in a single benchmark. It is about winning the customer base. Large enterprises are looking for alternatives to Nvidia to avoid vendor lock-in. Google's entry into this space provides that option. Revenue growth is tied to hardware sales. If TPU sales grow, Google can justify further investment in AI research. This creates a virtuous cycle. Revenue funds research, which improves hardware, which generates more revenue. The partnership with Marvell accelerates this cycle. Marvell brings established manufacturing relationships. This reduces the risk of production delays. Production delays cost money in downtime and lost sales. The companies aim to finalize the design of the memory processing unit as soon as next year. This timeline suggests urgency. Google's cloud division is under pressure to grow. Hardware sales are a way to accelerate that growth. Investors want to see revenue diversification. If cloud revenue relies solely on compute power, it is vulnerable to cyclical downturns. Selling specialized hardware like TPUs provides a more stable revenue stream. Google and Marvell did not immediately respond to a request for comment. This is standard for the industry. Companies rarely comment on early-stage negotiations. However, the leak itself confirms the direction of the partnership. Analysts have noted that Google needs to improve its hardware margins. If the TPU can be sold at a profit, it changes the financial equation for the entire company. Development timeline. The companies aim to finalize the design of the memory processing unit as soon as next year before handing it off for test production. This schedule is aggressive but realistic for a collaboration of this size. Google has a long history of internal chip design. Marvell has a long history of external chip design. Combining these capabilities reduces the learning curve. Test production is the next step. This involves manufacturing small batches to validate yield and performance. Yield rates are critical. If the new chips have a high defect rate, they will be unsellable. Google's internal use of TPUs is forgiving. A production chip must be flawless for external customers. The design finalization precedes handing off for test production. This sequence ensures that the architecture is stable before silicon fabrication begins. Reuters could not immediately verify the report. Verification is difficult in the semiconductor industry. Supply chain details are often confidential. However, the timing aligns with Google's broader strategy. The company has been reducing its reliance on Nvidia GPUs for internal tasks. The new chips are the culmination of that work. If the partnership fails, Google can still rely on internal design. If it succeeds, it opens new revenue channels. Google and Marvell did not immediately respond to a request for comment. This lack of comment does not negate the report. It simply means the companies are in the early stages of disclosure. In the tech industry, leaks often precede official announcements by weeks or months. The design timeline is public knowledge in the industry. The specific partnership is the variable. This partnership signals a shift in the AI hardware market. Nvidia's dominance is being challenged not just by new players, but by established ones like Google. The focus on efficiency and revenue generation indicates a mature understanding of the market. The new chips are not just faster processors. They are economic tools. By reducing the cost of running AI models, they make AI accessible to more applications. The design finalization precedes handing off for test production, ensuring a path to market. This is a significant development for the industry.

Marvell Technology achieved record data centre revenue of $6.1 billion in fiscal 2026, with custom silicon scaling to a $1.5 billion annual run-rate across 18 cloud-provider design wins. Google is now in active negotiations with Marvell for TPU development and LLM inference chip design services, according to FundaAI. The talks follow Nvidia's recent $2 billion strategic partnership with Marvell to develop custom XPUs and NVLink-compatible networking. Google's discussions aim to diversify suppliers and leverage Marvell's expertise in high-speed interconnects. Bloomberg projects Marvell could capture 20-25% of the $118 billion custom ASIC market by the early 2030s, potentially delivering $23.6-29.5 billion in annual revenue from this segment alone — more than triple its current total revenue.