Google

Runs Search and YouTube and builds Gemini AI

Senior CPU RTL Design Engineer - Subsystem

Silicon & ASIC DesignPosted on Nov 12

Full-timeNo salary listed

About the Job

Requirements

A bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
At least 8 years of experience in microprocessor architecture.
Experience in high-performance CPU or AI accelerator logic and RTL design or integration, including microarchitecture definition and PPA optimizations.
Experience integrating CPU and cache subsystems with SoCs.
Experience with a Hardware Description Language (HDL) and front-end design methodology.
Experience with RTL static checks, such as lint and clock-domain crossing (CDC).

Responsibilities

Participate in developing CPU or AI accelerator designs and delivering them into SoCs.
Develop CPU subsystem front-end designs, emphasizing microarchitecture and RTL design for the next-generation CPU.
Deliver designs that meet performance, power, area (PPA), and functional goals; interpret modern techniques into design constructs and languages; and participate in SoC integration.
Work closely with the functional verification team to ensure production-quality designs and with the physical design team to meet frequency, power, and area goals.
Contribute to all phases of complex CPU subsystem designs, from design specification to productization, including quality assurance and integration into the target system on a chip (SoC).
Collaborate with architecture, software, verification, power, design for test (DFT), and physical design teams to specify and coordinate delivery of high-quality register-transfer level (RTL) designs into SoCs.
Solve technical problems using microarchitecture and practical logic solutions, and evaluate design options with complexity, performance, power, area, and schedule in mind.

Desired Qualifications

Experience with the ARM instruction set architecture.
Experience with SoC design, architecture, and integration.
Experience with real-time operating systems, such as Android.
Experience with design for test (DFT), sensor integration, and debug architecture.

Participate in developing CPU or AI accelerator design and deliveries into SoC.
Develop CPU subsystem front-end designs, emphasizing on microarchitecture and RTL design for the next generation CPU.
Deliver designs that meet PPA and functional goals with modern techniques, interpret the techniques into design constructs, and languages in order to participate in SoC integration effort.
Work closely with the functional verification team to ensure production quality designs, and with the physical design team to meet frequency, power, and area goals.

Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience in microprocessor architecture.
Experience in high-performance CPU or AI accelerator logic/RTL design/integration including microarchitecture definition and PPA optimizations.
Experience in CPU and cache subsystem integration with SoCs.
Experience with a Hardware Description Language (HDL) and front-end design methodology.
Experience with RTL static checks (e.g., lint and CDC).

Preferred qualifications:

Experience with ARM Instruction set architecture.
Experience with SOC design, architect and integration.
Experience with real-time operating systems (e.g. Android).
Experience with DFT, sensor integration, debug architecture.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will contribute to all phases of complex designs of CPU subsystems from design specification to productization, including quality assurance and integration into target System on a chip (SoC). You will collaborate with members of architecture, software, verification, power, DFT, physical design, etc., to specify and coordinate delivery of high quality Register-Transfer Level (RTL) into SoC. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area and schedule in mind.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

In most instances, this position requires in-person interviews as part of the hiring process.

Google welcomes people with disabilities.

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: New Taipei, Banqiao District, New Taipei City, Taiwan; Zhubei, Zhubei City, Hsinchu County, Taiwan.

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
8 years of experience in microprocessor architecture.
Experience in high-performance CPU or AI accelerator logic/RTL design/integration including microarchitecture definition and PPA optimizations.
Experience in CPU and cache subsystem integration with SoCs.
Experience with a Hardware Description Language (HDL) and front-end design methodology.
Experience with RTL static checks (e.g., lint and CDC).

About the Company

Google

Runs Search and YouTube and builds Gemini AI

Google runs the world's most used search engine and free services such as YouTube, Android, and Gmail, and it builds the Gemini AI models that work inside them. In 2017, its researchers invented the transformer, the neural network design behind ChatGPT and most other AI chatbots. People use these services without paying, and Google earns most of its money from ads placed beside search results and YouTube videos. Businesses rent computing power and Gemini models through Google Cloud, and Google also sells subscriptions and Pixel phones. Larry Page and Sergey Brin founded Google in 1998 as Stanford PhD students; it is based in Mountain View, California, United States, and is the main business of parent company Alphabet.

Company size: 10,001+
Company stage: IPO
Headquarters: Mountain View, CA
Founded: 1998

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