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ASML

Manufactures photolithography systems for semiconductors

Electrical Safety Engineer

Full-TimeUpdated on 10/23/2026
$139.2k - $191.4k/yr
Mid, Senior
Bachelor's, Master's
San Jose, CA, USA
In PersonPrimary location: San Jose, CA; limited travel (<15%) with occasional collaboration across global teams.
Electrical Engineering
Company Does Not Provide H1B Sponsorship

About the job

Requirements
  • A Bachelor of Science in Electrical Engineering and 5+ years of electrical system design experience, or a Master of Science in Electrical Engineering and 2+ years of relevant experience.
  • Demonstrated experience applying electrical safety standards and conducting risk assessments in product design.
  • Experience in lab or manufacturing safety environments, including incident investigations, inspections, audits, and EHS management systems such as Intelex or similar systems.
  • Experience leading cross-functional safety initiatives without direct authority in complex equipment or industrial systems.
  • Experience mentoring or acting as a subject matter expert in electrical safety.
  • Strong understanding of electrical safety standards, including SEMI S2, IEC 60204-1, IEC 61010-1, NFPA 70, NFPA 70E, NFPA 79, OSHA, and UL.
  • Knowledge of safety risk assessment methodologies, including ISO 12100 and SEMI S10.
  • Experience with EHS processes and systems, including lab and safety inspections, 5S or 5S+1 implementation, incident investigation, and root cause analysis.
  • Experience using Intelex or similar EHS management systems for tracking incidents, audits, and corrective actions.
  • Deep technical expertise in electrical safety design principles and hazard mitigation.
  • Broad engineering knowledge to interface across disciplines.
  • Strong communication skills to tailor messaging to technical and non-technical audiences.
  • Ability to lead without authority and influence design decisions.
  • Ability to lead discussions, drive alignment, identify risks early, and deliver predictable outcomes.
  • Comfort operating with high-level managerial guidance and autonomy.
  • Ability to translate theoretical safety standards into practical design solutions.
Responsibilities
  • Independently lead technical discussions on test setup safety, identify risks, and propose mitigation strategies.
  • Maintain a broad understanding of safety domains, including dangerous gases, electrical safety, ergonomics, lifting, materials and substances, mechanical safety, radiation, thermal safety, and working at height.
  • Lead or contribute to incident and near-miss investigations, perform root cause analysis, and define corrective and preventive actions.
  • Conduct and support lab inspections to ensure compliance with EHS and electrical safety requirements.
  • Drive and sustain 5S+1 practices within labs and technical workspaces to improve safety, organization, and efficiency.
  • Ensure proper documentation, tracking, and closure of safety actions using the Intelex management system.
  • Represent EHS, including organizing monthly safety meetings with lab owners, to align design, operational, and workplace safety practices.
  • Work with New Product Introduction design teams to ensure compliance with electrical safety requirements defined in SAF documentation.
  • Identify key electrical safety risks early in development, before KD3, and drive mitigation strategies.
  • Define, propose, and lead Safety Risk Assessments, including identifying relevant topics and methodologies.
  • Participate in design reviews, including Critical Design Reviews, to ensure electrical safety requirements are met.
  • Ensure appropriate electrical safety verification strategies, including test methodologies and validation approaches.
  • Partner with Manufacturing and Customer Support to ensure safe operation and service of systems by leading risk assessments across New Product Introduction and the Installed Base lifecycle.
  • Act as the knowledge owner of electrical safety competence and provide guidance to engineering teams.
  • Apply electrical design expertise affecting human safety, including grounding, insulation, high-voltage systems, interlocks, and fault protection.
  • Define and maintain the electrical safety competence framework.
  • Develop and deliver training programs to improve electrical engineers’ safety awareness and competency.
  • Drive continuous improvement of organizational electrical safety maturity.
  • Maintain up-to-date knowledge of electrical safety standards and regulations.
  • Assess the impact of evolving standards and update SAF documentation to maintain compliance.

About the company

ASML designs and manufactures photolithography systems for semiconductor manufacturing. Its main products are deep ultraviolet (DUV) and extreme ultraviolet (EUV) lithography machines that print circuit patterns on silicon wafers, with EUV enabling smaller features. The company sells these systems to leading chipmakers and earns substantial revenue from installation, maintenance, and upgrades over the machines’ lifetimes. Its goal is to help continue scaling semiconductors by leading in high-end lithography and maintaining strong relationships with customers like TSMC, Samsung, and Intel.

Company Size

10,001+

Company Stage

IPO

Headquarters

Veldhoven, Netherlands

Founded

1984

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Simplify's Take

What believers are saying

  • Q2 2026 sales hit €9.3 billion, and full-year guidance rose to €43-45 billion.
  • Management said 2028 EUV output could exceed 110 tools, unlocking AI wafer capacity.
  • India launched ASML operations with Tata Electronics support, opening a new customer frontier.

What critics are saying

  • Europe bought zero ASML lithography tools in 2026, exposing a dead domestic demand base.
  • Chinese DUV entrants in Shanghai threaten ASML's 29% 2025 China revenue by 2027.
  • ASML cut 1,700 jobs in 2026; continued restructuring signals execution strain and morale damage.

What makes ASML unique

  • ASML alone ships EUV systems; no advanced chip node exists without Veldhoven tools.
  • High-NA EUV expands into Nvidia-scale data-center chips, extending ASML's moat through 2033.
  • Installed Base Management generated €2.8 billion in Q2 2026, deepening recurring revenue.

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Benefits

  • Flexible Work Hours
  • Remote Work Options

Growth & Insights and Company News

6 month growth

0%

1 year growth

0%

2 year growth

0%
Yahoo Finance
Oct 20th, 2026
Apple vs ASML: $416.2B revenue against 15.6% growth and a 29.4% margin

Apple and ASML offer two ways to bet on tech: one sells devices to billions of users, the other makes the lithography machines that chipmakers need to produce advanced semiconductors. In fiscal 2025, Apple's revenue reached nearly $416.2 billion, up about 6.4%. Net income was close to $112 billion, a 26.9% margin, and free cash flow was roughly $98.8 billion. Its debt-to-equity ratio was about 1.5. ASML reported revenue of nearly $36.8 billion, up 15.6%. Net income was $10.8 billion, a margin of about 29.4%, with free cash flow of roughly $12.5 billion. ASML's debt-to-equity ratio was about 0.2, and its current ratio was nearly 1.3, against Apple's 0.9.

Neoteo
Oct 16th, 2026
SemiAnalysis says ASML may be developing a hybrid-bonding tool.

SemiAnalysis says ASML may be developing a hybrid-bonding tool. A patent-based analysis describes a possible die-to-wafer process; ASML had not announced a tool as of October 15, 2026. October 16, 2026 Key points * 01 SemiAnalysis inferred that ASML may be developing a die-to-wafer hybrid-bonding tool; ASML had not announced it as of October 15, 2026. * 02 SemiAnalysis counted 27 ASML bonding patent families filed from December 2022 through November 2024, mostly related to D2W bonding. * 03 The proposed track-based process and its potential technical advantages are SemiAnalysis's interpretation, not measured tool results. * 04 SemiAnalysis expects advanced logic could be the first application; it forecasts D2W adoption in HBM no earlier than 2029, if it happens at all. SemiAnalysis says ASML may be developing a die-to-wafer hybrid-bonding tool. Its proposed process and potential impact on Besi remain unconfirmed. SemiAnalysis said on October 15, 2026, that ASML may be developing a die-to-wafer (D2W) hybrid-bonding tool, drawing that inference from patent filings, roadmap material and earlier reporting. ASML had not announced the tool as of the analysis. Read SemiAnalysis's analysis. Reuters reported on October 16 that ASML did not confirm the development and declined to comment on the report. Read the Reuters report. What the reporting says about ASML. SemiAnalysis counted 27 ASML bonding patent families filed between December 2022 and November 2024, most related to D2W bonding. It also cited The Elec reporting that ASML had begun architecture design with Prodrive Technologies and VDL ETG. These reports inform SemiAnalysis's inference; they do not amount to an ASML product announcement. The proposed tool is specifically a die-to-wafer bonder: individual semiconductor dies would be bonded to a wafer. The central claim in the coverage traces to SemiAnalysis's analysis. Investing.com summarized that analysis, while Reuters reported on it; those accounts do not constitute separate technical confirmation. How SemiAnalysis describes the proposed process. In SemiAnalysis's interpretation of patent material, each die would travel on an individual holder along a track, passing through inspection, cleaning, plasma activation, metrology and alignment before bonding to a wafer. The analysis suggests that independent shuttles could let stations work concurrently, that adding stations could increase capacity, and that recipes could accommodate different die types. Those are proposed design possibilities, not measured results. SemiAnalysis identifies alignment accuracy and particle control as potential advantages, while also pointing to engineering challenges involving feed-forward metrology, die-to-wafer contact, adapting non-bonding tools to the track and keeping the process loop clean. Why a possible tool could matter to Besi. SemiAnalysis describes Besi as the only supplier with D2W tools in volume production and says its logic-bonding business is concentrated at TSMC and Intel. If ASML develops a competing tool, Besi could face a new rival in that segment. SemiAnalysis expects advanced logic to be the likeliest first application for a prospective ASML tool. Its forecast for D2W bonding in high-bandwidth memory (HBM) is no earlier than 2029, if adoption happens at all. Other Languages Read this article in another available language.

MarketScreener
Oct 16th, 2026
Besi shares fall on report ASML is working on rival hybrid bonding product.

Besi shares fall on report ASML is working on rival hybrid bonding product. Published on 10/16/2026 at 06:54 am EDT - Modified on 10/16/2026 at 06:55 am EDT AMSTERDAM, Oct 16 (Reuters) - Shares in computer chip packaging equipment maker BE Semiconductor Industries (Besi) fell 3% on Friday after influential semiconductor research firm SemiAnalysis reported that one of the company's main growth products will face competition from bigger rival ASML. The SemiAnalysis report analysed 27 patent filings by ASML, which it said indicated ASML was developing a hybrid bonding product. Besi is a fraction of the size of ASML, the biggest maker of equipment used to make semiconductors, but Besi is a leader in hybrid bonding, an advanced packaging technology being used to create a new generation of more powerful three-dimensional chips. ASML has not confirmed it is developing such a tool. Besi did not respond to requests for comment. Besi shares were down 3% at EUR158.50, while ASML was up 1.1% at EUR1,480 in midday Amsterdam trading. A spokesperson for ASML declined to comment on the SemiAnalysis report but pointed to the company's launch of its first advanced packaging tool last year. "We continue to look at which directions the 3D integration industry will evolve... and where ASML's expertise can be of additional value," the company said in a statement at that time. In March, Reuters reported that ASML was planning additional packaging tools, citing Chief Technical Officer Marco Pieters in an interview. "The semiconductor market has already signalled that packaging is one of those next frontiers where performance gains can be unlocked, and ASML seems to be building next-gen tools headed in the same direction," said Nick Rossolillo, co-founder of Chip Stock Investor. "We see the new batch of packaging tools, beyond an EUV pipeline, as critical to pulling off the growth needed to justify (ASML's) elevated valuation." (Reporting by Toby Sterling; Editing by Susan Fenton) (C) Reuters - 2026

Channel NewsAsia
Oct 16th, 2026
Besi shares fall on report ASML is working on rival hybrid bonding product.

Besi shares fall on report ASML is working on rival hybrid bonding product. 16 Oct 2026 06:51PM (Updated: 16 Oct 2026 06:54PM) Add CNA as a trusted source to help Google better understand and surface our content in search results. AMSTERDAM, Oct 16: Shares in computer chip packaging equipment maker BE Semiconductor Industries (Besi) fell 3 per cent on Friday after influential semiconductor research firm SemiAnalysis reported that one of the company's main growth products will face competition from bigger rival ASML. The SemiAnalysis report analysed 27 patent filings by ASML, which it said indicated ASML was developing a hybrid bonding product. Besi is a fraction of the size of ASML, the biggest maker of equipment used to make semiconductors, but Besi is a leader in hybrid bonding, an advanced packaging technology being used to create a new generation of more powerful three-dimensional chips. ASML has not confirmed it is developing such a tool. Besi did not respond to requests for comment. Besi shares were down 3 per cent at €158.50, while ASML was up 1.1 per cent at €1,480 in midday Amsterdam trading. A spokesperson for ASML declined to comment on the SemiAnalysis report but pointed to the company's launch of its first advanced packaging tool last year. "We continue to look at which directions the 3D integration industry will evolve... and where ASML's expertise can be of additional value," the company said in a statement at that time. In March, Reuters reported that ASML was planning additional packaging tools, citing Chief Technical Officer Marco Pieters in an interview. "The semiconductor market has already signalled that packaging is one of those next frontiers where performance gains can be unlocked, and ASML seems to be building next-gen tools headed in the same direction," said Nick Rossolillo, co-founder of Chip Stock Investor. "We see the new batch of packaging tools, beyond an EUV pipeline, as critical to pulling off the growth needed to justify (ASML's) elevated valuation."

WZUU
Oct 16th, 2026
Besi shares fall on report ASML is working on rival hybrid bonding product.

Besi shares fall on report ASML is working on rival hybrid bonding product. By Thomson Reuters Oct 16, 2026 | 6:51 AM AMSTERDAM, Oct 16 (Reuters) - Shares in computer chip packaging equipment maker BE Semiconductor Industries (Besi) fell 3% on Friday after influential semiconductor research firm SemiAnalysis reported that one of the company's main growth products will face competition from bigger rival ASML. The SemiAnalysis report analysed 27 patent filings by ASML, which it said indicated ASML was developing a hybrid bonding product. Besi is a fraction of the size of ASML, the biggest maker of equipment used to make semiconductors, but Besi is a leader in hybrid bonding, an advanced packaging technology being used to create a new generation of more powerful three-dimensional chips. ASML has not confirmed it is developing such a tool. Besi did not respond to requests for comment. Besi shares were down 3% at €158.50, while ASML was up 1.1% at €1,480 in midday Amsterdam trading. A spokesperson for ASML declined to comment on the SemiAnalysis report but pointed to the company's launch of its first advanced packaging tool last year. "We continue to look at which directions the 3D integration industry will evolve... and where ASML's expertise can be of additional value," the company said in a statement at that time. In March, Reuters reported that ASML was planning additional packaging tools, citing Chief Technical Officer Marco Pieters in an interview. "The semiconductor market has already signalled that packaging is one of those next frontiers where performance gains can be unlocked, and ASML seems to be building next-gen tools headed in the same direction," said Nick Rossolillo, co-founder of Chip Stock Investor. "We see the new batch of packaging tools, beyond an EUV pipeline, as critical to pulling off the growth needed to justify (ASML's) elevated valuation." (Reporting by Toby Sterling; Editing by Susan Fenton) Now Playing WZUU 92.5 - Kalamazoo's Music Authority Fri Oct 16 Kalamazoo, MI, USA Wind/Dir: 30 MPH-NW Humidity: 94%