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AMD

Designs chips for computers and AI systems

Packaging Engineer

Hardware EngineeringConfirmed live in the last 24 hours
Full-timeHsinchu, Hsinchu City, TaiwanNo salary listedIn-person

About the Job

Requirements

  • A bachelor's degree or higher in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • Five or more years of experience in semiconductor packaging or system-on-chip physical design automation is preferred.
  • Strong working knowledge of electronic design automation packaging tools such as Cadence APD/SiP, Siemens Xpedition, and Synopsys 3DICC or equivalent is preferred.
  • Expertise in scripting and automation using Python, Tcl, SKILL, or C++ is preferred.
  • Experience applying artificial intelligence or machine learning techniques to engineering or design workflows is preferred.
  • Familiarity with frameworks such as PyTorch or TensorFlow is preferred.
  • Understanding of advanced packaging technologies such as 2.5D/3D IC, chiplets, heterogeneous integration, and bridge/interposer-based architectures is preferred.
  • Familiarity with design verification flows (DRC/LVS), parasitic extraction, and signal integrity/power integrity fundamentals is preferred.
  • Experience working with cross-functional teams in Design, SI/PI, Mechanical, and EDA is preferred.
  • Ability to translate complex design challenges into scalable automation solutions.
  • Ability to work effectively across Design, EDA, and AI/ML teams.
  • Ability to operate with limited supervision and deliver high-quality results aligned to project goals.
  • Ability to collaborate across internal and external stakeholders in a multidisciplinary environment.

Responsibilities

  • Develop, deploy, and maintain automation frameworks and AI-assisted workflows for package substrates, silicon interposers, and bridge-based integration.
  • Apply AI/ML methodologies to enhance design activities such as auto-routing and placement optimization, signal integrity and power delivery improvements, and design rule compliance and verification.
  • Collaborate with the package design team to identify high-impact automation opportunities, reduce manual design effort and cycle time, and improve design robustness and quality.
  • Partner with EDA tools teams and vendors to implement automation features, enhance tool capabilities and workflows, and support next-generation advanced packaging design enablement.
  • Develop automation and tools for design-flow integration, data extraction and analysis, and closed-loop optimization with simulation teams.
  • Support execution of design milestones and tape-outs, ensuring automation readiness and quality.
  • Contribute to documentation, best practices, and reusable workflows for broader team adoption.

Desired Qualifications

  • Five or more years of experience in semiconductor packaging or system-on-chip physical design automation.
  • Strong working knowledge of EDA packaging tools such as Cadence APD/SiP, Siemens Xpedition, and Synopsys 3DICC or equivalent.
  • Expertise in scripting and automation using Python, Tcl, SKILL, or C++.
  • Experience applying AI/ML techniques to engineering or design workflows; familiarity with PyTorch or TensorFlow.
  • Understanding of advanced packaging technologies such as 2.5D/3D IC, chiplets, heterogeneous integration, and bridge/interposer-based architectures.
  • Familiarity with design verification flows (DRC/LVS), parasitic extraction, and SI/PI fundamentals.
  • Experience working with cross-functional teams in Design, SI/PI, Mechanical, and EDA.

About the Company

AMD

Designs chips for computers and AI systems

AMD designs processors, graphics chips and AI accelerators for computer makers, cloud operators and businesses that build electronic devices. Its Ryzen processors power personal computers, while EPYC processors handle work in data centers and Radeon chips render graphics. Instinct accelerators run AI models, paired with software that developers use to train models and put them into production. AMD sells chips and related computing systems through equipment makers, distributors and retail channels, and contracts with outside foundries to fabricate its semiconductor designs. It was founded in 1969 and has its headquarters in Santa Clara, California.

Company size
10,001+
Company stage
IPO
Headquarters
Santa Clara, CA
Founded
1969

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