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Synopsys

EDA software for chip design

Senior Staff Engineer

Hardware Validation & TestingUpdated on Nov 9
Full-timeSouth KoreaNo salary listedIn-person

About the Job

Requirements

  • A bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, and 10 or more years of hands-on semiconductor verification experience.
  • Expert-level knowledge of semiconductor verification methodologies, with extensive hands-on experience in SystemVerilog, UVM, and industry-standard verification flows, tools, and environments.
  • Strong programming and scripting skills in Python, Perl, or similar languages, with a track record of building verification automation, tools, or infrastructure that improved team productivity.
  • Ability to debug complex verification failures across RTL, testbenches, and simulation environments.
  • Strong analytical and problem-solving skills.
  • Ability to take ownership of verification challenges end to end, from understanding user needs through building and deploying solutions in production environments.
  • Ability to build tools and automation that verification engineers will use, grounded in understanding their workflows, pain points, and what will help without adding overhead.
  • Ability to communicate technical concepts clearly to verification engineers and cross-functional teams, explaining complex tradeoffs without losing critical details.
  • Ability to share knowledge through documentation, code reviews, and collaboration.
  • Ability to work effectively across global teams and time zones, building trust through clear communication and reliable delivery.

Responsibilities

  • Design, develop, and deploy AI-driven automation solutions that improve verification productivity and address engineering challenges.
  • Collaborate with cross-functional teams to understand user needs, identify workflow bottlenecks, and develop scalable solutions that improve engineering efficiency and user experience.
  • Integrate new technologies and capabilities into existing verification workflows and tools, creating experiences that fit how engineers work.
  • Evaluate emerging technologies, including AI and machine learning approaches, and assess their applicability to engineering problems through prototyping and user validation.
  • Provide technical leadership on verification productivity initiatives, contributing to architecture decisions, tool development, and engineering best practices.
  • Reduce verification cycle time and debug hours by delivering automation and tools that eliminate repetitive work and surface insights faster.
  • Improve verification quality and consistency by building frameworks and methodologies that help catch issues earlier and support systematic work.
  • Accelerate debug workflows by creating tools to analyze simulation data, correlate failures, and identify root causes more quickly.
  • Help verification engineers focus on high-value problem-solving by automating routine workflow tasks.
  • Contribute to the verification technology roadmap by exploring approaches and technologies that could improve verification productivity.
  • Build solutions adopted and used daily by verification teams, creating measurable improvements in productivity and engineer satisfaction.

Desired Qualifications

  • An MS or PhD is preferred.
  • Interest in or exposure to AI, machine learning, or automation technologies.

About the Company

Synopsys

EDA software for chip design

Synopsys provides software tools and services for electronic design automation (EDA), helping engineers design, simulate, verify, and optimize semiconductor chips and systems. Its products cover the full design flow, including RTL-to-gating synthesis, place-and-route, timing analysis, verification, and silicon validation, as well as software integrity solutions and hardware-assisted verification. Engineers use these tools to model, simulate, and validate complex chip designs before manufacturing, reducing bugs and improving performance. Compared with many competitors, Synopsys differentiates itself through its broad, end-to-end design toolchain, large ecosystem of IP and integration with simulation and modeling capabilities gained from its 2025 merger with ANSYS, and its global scale and support. The company aims to help designers push the boundaries of chip and system performance, accelerate time-to-market, and enable silicon-to-systems design across a wide range of industries.

Company size
10,001+
Company stage
IPO
Headquarters
Sunnyvale, CA
Founded
1986

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