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Rambus

Licenses high-speed chip-to-chip connectivity IP

Senior Member of Technical Staff Layout Design

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeBengaluru, Karnataka, India

About the Job

Requirements

  • A master's degree in Electrical or Electronic Engineering, or equivalent, and at least 5 years of relevant experience.
  • Experience with layout design at 22 nm and FINFET nodes of 16 nm, 12 nm, and 7 nm.
  • Knowledge of double patterning, device matching, signal shielding, layout parasitics, and layout-dependent effects.
  • Fundamental knowledge of semiconductor device physics, cross-sections, and construction.

Responsibilities

  • Design the layout of assigned blocks using Cadence Virtuoso XL/VXL features.
  • Perform layout verification checks, including LVS, DRC, antenna, and density checks, using Calibre.
  • Collaborate with designers to resolve layout issues.
  • Fix reliability issues involving EMIR and ESD/latch-up.
  • Apply standard layout practices for layout matching, parasitics, noise and noise isolation, supply considerations, latch-up, shielding, wells, substrates, and isolation.
  • Collaborate with analog designers across the globe to solve challenging problems.

Desired Qualifications

  • Layout design experience with transmitters, receivers, PLLs, clocking, PI, bandgap, and voltage regulators.
  • Knowledge of SKILL, Perl, or Tcl scripting.

About the Company

Rambus

Licenses high-speed chip-to-chip connectivity IP

Rambus designs, develops, and licenses high-speed chip-to-chip connectivity technology. Its IP powers data center servers, AI accelerators, and automotive systems, and is licensed to other semiconductor companies rather than manufactured and sold directly. The products are high-speed interfaces and security features embedded in chips, enabling fast, reliable communication between components. Rambus differentiates itself through a licensing-based model focused on advanced IP for memory, security, and high-speed interfaces across data centers, AI, and automotive markets, rather than relying on a traditional product lineup. The company’s goal is to enable high-performance chip communication at scale by monetizing its intellectual property through licensing and expanding into growing markets like data centers, AI, and automotive.

Company size
1,001-5,000
Company stage
IPO
Headquarters
San Jose, CA
Founded
1990

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