Senior Emulation Engineer

Salary Range: 200000 to 300000 (Currency: USD) (Pay period: per-year-salary)

Role Overview

Responsibilities

Set up, own, and maintain emulation flows for the Velaura SoC on Palladium, Veloce, and/or Zebu.

Bring up designs on the emulator, resolving compile/elaboration, capacity/partitioning, and design-mapping issues.

Build and maintain regression flows, optimizing compile time, run time, throughput, and capacity utilization.

Support HW/SW co-verification and pre-silicon software bring-up—firmware, drivers, runtime, and OS.

Optimize on-emulator debug (waveform capture, triggers, visibility) and drive fast root-cause analysis across HW/SW.

Verify performance, latency, bandwidth, QoS, and real-time behavior under representative workloads.

Partner with architects, RTL, and verification engineers on emulation strategy, transactor requirements, and coverage goals.

Emulate compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other core SoC infrastructure.

Build automation, scripting, and CI hooks for compile and regression pipelines.

Contribute to FPGA prototyping, pre-silicon validation, and post-silicon debug.

Apply modern tools, including AI-assisted verification and debug, to improve productivity, quality, and coverage.

Contribute to a culture of technical excellence and continuous improvement.

Required Qualifications

10+ years in hardware emulation and/or verification of complex digital systems.

Hands-on experience setting up emulation flows on Palladium, Veloce, or Zebu.

Ability to debug compile and elaboration issues on emulation platforms.

Proven ability to set up and optimize emulation regression flows for faster turnaround.

Strong analytical and problem-solving skills.

Strong grasp of computer, micro-, and SoC architecture and digital design fundamentals.

Solid understanding of CDC, clocking, and reset behavior in emulation bring-up.

Experience with SystemVerilog, UVM, C/C++, transactors, and assertions.

Understanding of memory systems, interconnects, caches, DMA engines, processors, or accelerators.

Experience debugging complex system-level issues across hardware and software.

Strong scripting and automation skills for build, regression, and CI pipelines.

Ability to work effectively in a multidisciplinary team.

Preferred Qualifications

Experience with design partitioning, capacity optimization, and multi-FPGA/multi-board emulation scaling.

Experience with FPGA prototyping and pre-silicon software bring-up environments.

Experience with HW/SW co-verification and system-level validation.

Familiarity with low-power methodologies and their verification/emulation criteria.

Experience with AI, machine learning, or edge AI hardware.

Familiarity with robotics, drones, autonomous vehicles, or industrial automation systems.

Experience verifying or emulating QoS, latency-sensitive, or real-time systems.

Exposure to performance modeling, profiling, and workload characterization.

Experience with one or more of the following standards: ISO 26262, IEC 61508, IEC 61511, ISO 13849.

Experience using modern AI tools and workflows to accelerate engineering productivity.

Background in CPUs, GPUs, AI accelerators, networking and communications silicon, storage and data movement architectures, robotics and autonomous systems, automotive and ADAS platforms, aerospace and defense systems, real-time and safety-critical computing, or functional safety architectures and methodologies.