RosaicLabs

Custom x86 chips using Atom RTL

AI Accelerator Design Verification Engineer

Hardware Validation & TestingConfirmed live in the last 24 hours

Full-time$125k - $250k /yr

About the Job

Requirements

A bachelor's or master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
A strong foundation in AI accelerator and computer architecture and digital design, including tensor cores and SIMT/SIMD/vector processing; floating-point and computer arithmetic, including reduced-precision formats; on-chip memories, scratchpads, and DMA engines; cache hierarchy, memory systems, and HBM/DRAM interfaces; network-on-chip and on-chip interconnects; and dataflow, scheduling, and synchronization across many compute cores.
Working knowledge of modern AI accelerator flows and instruction set architectures, including familiarity with instruction set architecture simulators or reference models.
Proficiency in SystemVerilog, C/C++, and assembly.
Hands-on experience using agentic AI tools across the engineering workflow, including delegating multi-step tasks to agents, writing clear instructions and context, and critically checking agent results.
Scripting experience for automation, test generation, regression management, or data analysis, such as Python, Tcl, or Rust.

Responsibilities

Develop verification plans for AI accelerator blocks, including tensor processing, fabric/network-on-chip, and system-on-chip flows.
Write and debug SystemVerilog/UVM testbenches, checkers, stimulus, scoreboards, and reference models for an assigned block or subsystem.
Build emulation-friendly testbenches using synthesizable, transactor-based environments that run the same tests in simulation and on emulators or FPGA prototypes.
Use agentic AI tools across the verification workflow to generate test plans from specifications, write and review testbench code, triage regression failures, root-cause bugs, and analyze coverage; review and validate all agent output.
Verify numerical correctness of compute datapaths (FP*) against bit-accurate golden models.
Run real machine-learning kernels and random programs on RTL, co-simulated against an instruction set architecture or architectural reference model.
Define, implement, and close functional and code coverage goals, analyze coverage holes, and drive them to closure.
Debug failures across RTL, testbenches, and reference models, and work with RTL designers to root-cause and resolve bugs.
Apply formal verification, assertions (SVA), and emulation where appropriate to improve verification quality and efficiency.
Run and maintain regressions across simulation, emulation, and FPGA platforms, and track bug trends and verification progress metrics.
Partner with RTL design, performance modeling, CAD/methodology, and software teams to align verification strategy, improve tools and flows, and drive shared quality, schedule, and tape-out goals.
Participate in microarchitecture, RTL, and verification reviews, and write technical documentation.

Desired Qualifications

Familiarity with emulation-friendly verification, including synthesizable testbenches and transactors.
Exposure to machine-learning frameworks or workloads such as PyTorch, TensorFlow, or ONNX.

Salary Range: 125000 to 250000 (Currency: USD) (Pay period: per-year-salary)

Join our hardware team as AI Accelerator Design verification engineer verifying the state of the art AI chip, with hands-on ownership of verification environments from test plan through coverage closure and SI bring-up.

What you'll do

Develop verification plans for AI accelerator blocks: tensor processing, fabric / network-on-chip, and SoC flows
Write and debug SystemVerilog/UVM testbenches, checkers, stimulus, scoreboards, and reference models for your assigned block or subsystem
Build emulation-friendly testbenches: synthesizable, transactor-based environments that run the same tests in simulation and on emulators or FPGA prototypes
Use agentic AI tools across the verification workflow: generating test plans from specifications, writing and reviewing testbench code, triaging regression failures, root-causing bugs, and analyzing coverage. Review and validate everything the agents produce.
Verify numerical correctness of compute datapaths (FP*) against bit-accurate golden models
Run real ML kernels and random programs on the RTL, co-simulated against an ISA/architectural reference model
Define, implement, and close functional and code coverage goals, analyzing holes and driving them to closure
Debug failures across RTL, testbench, and reference models, and work with RTL designers to root-cause and resolve bugs
Apply formal verification, assertions (SVA), and emulation where appropriate to improve verification quality and efficiency
Run and maintain regressions across simulation, emulation, and FPGA platforms, and track bug trends and verification progress metrics
Partner with RTL design, performance modeling, CAD/methodology, and software teams to align on verification strategy, improve tools and flows, and drive shared quality, schedule, and tape-out goals
Participate in microarchitecture, RTL, and verification reviews, and write technical documentation

What we're looking for

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science or a related field.
Strong foundation in AI accelerator and computer architecture and digital design, with solid understanding of following:
Tensor cores and SIMT / SIMD / vector processing
Floating-point / computer arithmetic, including reduced-precision formats
On-chip memories, scratchpads, and DMA engines
Cache hierarchy, memory systems, and HBM/DRAM interfaces
Network-on-chip and on-chip interconnects
Dataflow, scheduling, and synchronization across many compute cores
Working knowledge of modern AI accelerator flows and ISAs, including familiarity with ISA simulators or reference models
Proficiency in System Verilog, C/C++, assembly
Familiarity with emulation-friendly verification (synthesizable testbenches, transactors) is a plus
Hands-on experience using agentic AI tools across the engineering workflow: delegating multi-step tasks to agents, writing clear instructions and context, and checking their results critically
Scripting experience for automation, test generation, regression management, or data analysis, such as Python, Tcl, or Rust
Exposure to ML frameworks or workloads (PyTorch, TensorFlow, or ONNX) is a plus

About the Company

RosaicLabs

Custom x86 chips using Atom RTL

RosaicLabs designs customized processors by licensing Intel’s Atom technology, including RTL, and integrating an Intel x86 core into its own chip designs. The company, based in Santa Clara, operates in stealth mode and aims to build specialized SoCs for targeted workloads, especially in edge and mobile scenarios where energy efficiency matters. The business model hinges on a strategic agreement with Intel that grants access to core IP and RTL, enabling Rosaic to tailor chips for specific applications rather than using off-the-shelf processors. This arrangement also serves as a potential pathway for Intel to monetize its x86 IP and attract new customers for its foundry services. Rosaic’s goal is to create custom silicon platforms that leverage the established x86 software ecosystem while delivering low-power, efficient computing at the edge.

Company size: 1-10
Company stage: Not listed
Total funding: Not listed
Headquarters: Not listed
Founded: Not listed

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