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Broadcom

Designs chips and software for data centers

DFT Lead Engineer

Hardware Validation & TestingConfirmed live in the last 24 hours
Full-timeSan Jose, CA, USAIn-person

About the Job

Requirements

  • Bachelor's degree in Electrical, Electronic, or Computer Engineering and 12+ years of relevant industry experience, or a Master's degree in those fields and 10+ years of relevant industry experience.
  • Strong Design for Test (DFT) background, such as input/output and analog DFT, automatic test pattern generation (ATPG), scan, and built-in self-test (BIST).
  • Experience with scan insertion and scan compression using tools such as DFT Compiler or Mentor TestKompress.
  • Knowledge of ATPG vector generation, simulation, and debugging using tools such as TetraMax or Fastscan.
  • Experience with Verilog coding, testbench generation, and simulation.
  • Experience inserting and verifying memory BIST for embedded SRAM, CAM, eDRAM, and ROM.
  • Experience verifying boundary scan and generating test vectors, with knowledge of IEEE 1149.1 and IEEE 1149.6.
  • Basic knowledge of test static timing analysis (Test-STA) and constraints.
  • Strong background in IEEE 1687, IJTAG, ICL, and PDL.
  • Ability to work in a multidisciplinary, cross-department environment.
  • Knowledge of analog and digital circuit design and device physics fundamentals.
  • Understanding of silicon processing, logical and physical synthesis, and transistor reliability principles.
  • Ability to code using Tcl, Perl, Ruby, Python, C++, or similar languages.

Responsibilities

  • Understand Broadcom and customer DFT feature requirements and DPPM goals, and define appropriate DFT specifications for the ASIC.
  • Implement DFT, including scan, MBIST, TAP, LBIST, input/output, SerDes, and other input/output DFT integration.
  • Work closely with STA and DI engineers on design closure for test.
  • Generate, verify, and debug test vectors before tape release.
  • Validate and debug test vectors on ATE during silicon bring-up.
  • Assist with silicon failure analysis, diagnostics, and yield-improvement efforts.
  • Interface with customers and physical design and test engineering/manufacturing teams located globally.
  • Work closely with input/output DFT engineers and other stakeholders.
  • Debug customer-returned parts on ATE.
  • Develop DFT solutions to solve testability problems in 7 nm and beyond.
  • Automate DFT and test-vector-generation flows.

Desired Qualifications

  • Experience working on ATE.
  • Experience with SerDes, DDR, PCIe, Ethernet, and CXL IOBIST verification and silicon debugging.
  • Experience working on Tessent SSN.

About the Company

Broadcom

Designs chips and software for data centers

Broadcom designs chips and sells infrastructure software for the companies that run large data centers, telecom networks and corporate IT. Its custom AI processors, built with cloud companies, and its Ethernet switch chips move and process data inside the computer clusters that train AI models. The chip business also makes parts for broadband, wireless, storage and industrial equipment, sold to device makers and cloud operators, while VMware software lets businesses run private clouds and is sold by subscription. Broadcom took its current form in 2016, when Avago Technologies, formed in 2005 from Agilent's chip unit, bought Broadcom Corporation, and it is based in Palo Alto, California.

Company size
10,001+
Company stage
IPO
Headquarters
Palo Alto, CA
Founded
2005

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