Senior Engineer - Constraints / SDC Engineer

At Quest Global, it’s not just what we do but how and why we do it that makes us different. With over 25 years as an engineering services provider, we believe in the power of doing things differently to make the impossible possible. Our people are driven by the desire to make the world a better place—to make a positive difference that contributes to a brighter future. We bring together technologies and industries, alongside the contributions of diverse individuals who are empowered by an intentional workplace culture, to solve problems better and faster.

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Key Responsibilities

• Own and manage timing constraints (SDC) development and maintenance for complex SoC designs.
• Define and manage clocks, clock relationships, and timing exceptions using XML-based or equivalent constraint methodologies.
• Develop, review, and validate timing constraints with strong focus on quality and accuracy.
• Independently manage and enhance constraint build flows and automation methodologies.
• Perform debug and analysis related to GCA, TCM, minimum pulse width, and minimum period violations.
• Collaborate closely with Physical Design (PD) teams to address ad-hoc constraint development and timing closure requirements.
• Analyze design specifications and translate functional/timing requirements into robust timing constraints.
• Drive constraint signoff activities and ensure timing intent is accurately captured throughout the design cycle.

Required Skills

• Strong expertise in SDC creation, timing constraint development, and validation.
• Good understanding of clock architecture, generated clocks, clock groups, and timing relationships.
• Hands-on experience with constraint verification, timing analysis, and debug methodologies.
• Ability to independently build, maintain, and troubleshoot constraint flows.
• Experience in debugging GCA/TCM issues and handling min pulse width and min period checks.
• Strong analytical and problem-solving skills with the ability to work on challenging timing scenarios.
• Good understanding of digital design and static timing analysis (STA) concepts.

Preferred Qualifications

• Experience with SerDes-based protocols and high-speed interfaces.
• Ability to interpret protocol specifications and develop timing constraints based on documented requirements.
• Familiarity with advanced SoC design flows and industry-standard STA tools.

Experience

• Typically 5+ years of experience in Timing Constraints, STA, or Physical Design support roles within VLSI/ASIC development environments.

We are known for our extraordinary people who make the impossible possible every day. Questians are driven by hunger, humility, and aspiration. We believe that our company culture is the key to our ability to make a true difference in every industry we reach. Our teams regularly invest time and dedicated effort into internal culture work, ensuring that all voices are heard.

We wholeheartedly believe in the diversity of thought that comes with fostering a culture rooted in respect, where everyone belongs, is valued, and feels inspired to share their ideas. We know embracing our unique differences makes us better, and that solving the worlds hardest engineering problems requires diverse ideas, perspectives, and backgrounds. We shine the brightest when we tap into the many dimensions that thrive across over 21,000 difference-makers in our workplace.