Circuit Validation Engineer

 Silicon Co-Design Group (SCG) is a wide-ranging, multi-functional, integral team at NVIDIA. We sit at the crossroads of design, architecture, marketing, operations, and productization. Our contributions span from the arch stage and extend to defining final products. We architect innovative solutions for Datacenter, Server, Gaming, Robotics, Automotive, and Embedded markets. We are fast-paced, dynamic, share a sense of humor, and collaborate extensively to push the boundaries of what is possible. We do all of this with an eye on making groundbreaking, impactful market disruptions! We are looking for a Circuit Validation Engineer(NCG) to define and validate circuit methodologies across GPUs and SoCs, validate circuit behavior, performance, quality, and product readiness. This is a highly visible, multi-functional role focused on building methodologies that help products meet SOL(Speed Of Light) milestones and achieve the high NVIDIA quality bar our customers expect.

What you will be doing:

• Standing up silicon co-design prototypes and measurement setups that expose power-rail noise, circuit enablement and tuning, performance, and volume behavior — from first bring-up through repeatable experiments that others can rerun.
• Planning and executing design of experiments (DOE): choosing factors and ranges (voltage, frequency, workload, temperature, process), defining sample plans and success criteria, and analyzing main effects and interactions so results are usable, not just collected.
• Building Python pipelines and analyses that turn prototype, DOE, simulation, and characterization data (power, noise, Vmin/Fmax, binning yield) into traces, summaries, and inputs for firmware tuning, product specs, and manufacturing limits — with checks for schema, units, corners, and SKU mapping.
• Partnering with architecture, design, validation, and firmware to add debug hooks, iterate the prototype, and document what the experiment proved versus what still needs silicon char
• Using secure, traceable, validated AI-assisted workflows for experiment planning, analysis, and documentation, with human oversight on any conclusion that could affect limits, bins, or specs.

What we need to see:

• MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Background in a related silicon, validation, characterization, productization (SoC, GPU, CPU, or similar).
• Working knowledge of silicon circuit/clock/power/noise concepts — for example DVFS, Vmin/Fmax, shmoo, PDN/noise, Driver, or margins — and comfort with learning DOE and prototype bring-up in a co-design setting.
• Hands-on experience with at least one of: lab or post-silicon bring-up, experiment or characterization campaigns or manufacturing test/limits that consume chip data.
• Proficiency in Python (or similar) for data analysis, automation, and validation; comfort with Git and structured test/regression. SQL or lightweight dashboards are a plus.
• Ability to turn an ambiguous silicon question into a measurable experiment, communicate clearly across teams, and write notes others can execute from.
• Strong AI-enabled skills and thinking — use AI to accelerate analysis, exploration, and documentation while maintaining rigor, originality, and judgment that do not come from AI.

Ways to stand out from the crowd:

• You have run a test-chip, prototype vehicle, or characterization DOE and can explain what you would change in the next matrix.
• Direct experience on GPU/SoC/CPU circuits, power, performance, PDN/noise, or sim-to-silicon correlation.
• You have shipped an internal tool, dashboard, or data pipeline (Python, databases, web apps) that other people actually use.
• Hands-on LLMs in an engineering workflow — agents, RAG, or evaluation — including a time you had to debug a incorrect or unsafe answer.
• Exposure to firmware/BIOS parameters, eFuse/limits, or ATE/SLT screening, and how they connect to product SKUs.