Requirements

14nm process knowledge and experience
Genesys and Genoa layout editors (Genesys, Genoa)
Voltage regulators and Low Dropout Regulators design understanding
At least 4–8 years of experience in understanding and independently handling analog and mixed-signal blocks such as LDOs, switching regulators, data converters, phase-locked loops, SerDes, LVDS, and top-level layout integration of AMS blocks
Good understanding of deep sub-micron layout techniques and issues in CMOS process technology nodes such as 14nm, 22nm, 16nm FinFET technologies
Experience in Genesys / Genoa layout editor, AAPR flow, Helix
Good debugging skills in physical verification checks like LVS, DRC, DFM, ANTENNA, ERC, SOFT, OPC
Deep understanding of reliability analysis in layout such as electromigration, IR drop, latch-up, ESD using Apache tools
Knowledge of CMOS and FinFET processes and fabrication
Scripting languages such as Perl or Tcl; plus is noted
Full-chip integration and verification experience
Good team player with excellent communication skills interfacing with the circuit team
Layout design, verification, post-layout fixes and sign-off of high performance analog and mixed-signal blocks and IO/high-speed IO blocks
Mask Design team lead for client engagement
Interface with the Circuit Design team onsite
Proficiency in industry-standard EDA tools such as Cadence (Virtuoso-L, Virtuoso-XL, PVS & QRC), Mentor Graphics (Calibre & XRC), and Hercules

Responsibilities

Layout design, verification, post-layout fixes and sign-off of high-performance analog and mixed-signal blocks and IO/high-speed IO blocks
Mask Design team lead for the client engagement
Interface with the circuit design team onsite
Interfacing with the circuit team to ensure design and fabrication alignment
Engage in mask data preparation and sign-off activities for production runs
Collaborate with the circuit design team to optimize AMS blocks for performance, area, and power

Desired Qualifications

Mask Design Engineer

STEM Xpert