Senior FPGA Design Verification Engineer

Basic Qualifications

Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 8 years of relevant experience; or Master's degree plus a minimum of 6 years of relevant experience.

CLEARANCE REQUIREMENTS:Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.

Responsibilities for this Position

We encourage you to apply if you have this advanced expertise or experience:

• UVM Architecture: Proven capability to design, build, and scale advanced verification environments from the ground up using SystemVerilog and Universal Verification Methodology (UVM).
• Component Development: Expert-level capability in developing complex UVM components including reusable agents, test sequences, predictive reference models, and scoreboards.
• Protocols & Interfaces: Strong working knowledge of high-speed protocols and interfaces such as AXI protocols, PCIe, and Ethernet.
• Verification Metrics: Experience in establishing comprehensive functional coverage, structural code coverage targets, and writing Assertions.
• Traceability: Familiarity with requirements-based verification, requirement tracing, and developing requirement verification strategies.
• Simulation Tools: Deep understanding of RTL simulation platforms within a Linux Environment (Familiarity with Siemens Questa Advanced Functional Verification tools is a plus).
• Automation & Scripting: Experience in scripting to automate full verification suites and regression pipelines (e.g., Python, Tcl, Bash/Csh, or Perl).

Familiarity with the following are also helpful (Nice-to-Have):

• Verification IP: Experience integrating and configuring Questa Verification IP (QVIP).
• Hardware Co-Design: Prior FPGA/ASIC microarchitecture or design experience.
• Vendor Ecosystems: Deep familiarity with Xilinx toolchains including Vivado, Vitis, and verifying designs targeting Xilinx IP and SoC architectures.
• Advanced Infrastructure: Experience using/configuring Continuous Integration (CI/CD) pipelines within GitLab for regression automation.
• Advanced Methods: Exposure to the Register Abstraction Layer (RAL) or Formal Verification tools.
• Version Control: Proficiency with GIT/GitLab Version Control System.

Duties and Tasks:

• Methodology Ownership: Define the technical verification methodology and architectural strategy for complex, multi-million gate FPGAs.
• Full-Lifecycle Verification: Analyze system requirements to drive requirements-based verification, requirement tracing, and the creation of execution-focused test plans.
• Test Implementation: Implement complex test cases and manage nightly regressions.
• Lab Issue Triage: Collaborate with the team when physical hardware issues are discovered, reproducing lab anomalies within the simulation environment to enable efficient design debugging.
• Project Execution: Plan, scope, and independently execute complex project tasks tied to core business milestones.
• Technical Leadership: Serve as a mentor and provide technical direction to junior verification engineers on the team.

General Knowledge, Skills, and Abilities:

• Cross-Functional Support: Ability to collaborate and interface with project leaders and other professionals within the Engineering department and with project teams across the company.
• Agility: Ability to multi-task and thrive in a dynamic, fast-paced environment with evolving technical requirements.
• Analytical Mindset: Strong creative problem-solving skills to anticipate systemic edge cases and uncover deep architectural design flaws.

Salary Note

This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.

Combined Salary Range

USD $176,052.00 - USD $195,000.00 /Yr.

Company Overview

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!

Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans