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Micron Technology

Makes memory and storage chips for AI and PCs

HBM 3D Power Delivery Network Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeIn-person

About the Job

Requirements

  • Strong experience in power delivery network design and analysis for complex SoCs or high-performance ASICs.
  • Proficiency with EM/IR analysis tools such as RedHawk, Totem, or equivalent.
  • Proficiency with Spice-based simulation tools and 3D modeling of PDN networks.
  • Solid understanding of IR drop, electromigration, dynamic voltage droop, and power noise mechanisms.
  • Experience with physical design flows and close interaction with floorplanning, routing, and implementation teams.
  • Familiarity with the full RTL-to-GDSII design flow and signoff methodologies.
  • A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field is preferred.
  • A minimum of 10 years of experience in a related field is required.

Responsibilities

  • Design and develop SoC-level and HBM-cube-level power delivery networks for HBM designs, including power grid architecture, routing strategies, and decoupling schemes.
  • Perform EM/IR analysis and optimization using industry-standard tools such as Cadence RedHawk and Ansys Totem to ensure power integrity across dynamic workloads.
  • Collaborate with physical design teams on floorplanning, placement, and routing strategies to enable efficient PDN implementation.
  • Drive power integrity closure across multi-mode/multi-corner scenarios, identifying and mitigating droop, noise, and electromigration risks.
  • Work with package and system teams to co-optimize die-package-system PDN interactions, including bump/pad assignment and current distribution.
  • Develop and validate power models, including activity-based current profiles and transient analysis for realistic workload scenarios.
  • Partner with architecture and design teams to influence power-aware design decisions, including power domains, gating strategies, and current demand shaping.
  • Support signoff activities, including EM, IR, and reliability verification, ensuring the design meets long-term reliability and manufacturability goals.
  • Debug and root-cause PDN-related issues during pre-silicon and post-silicon phases, including silicon correlation and model refinement.
  • Improve PDN methodologies through automation, scripting, and best-practice development across HBM programs.

Desired Qualifications

  • Experience with HBM, DRAM, or memory-centric SoC designs, including understanding of 3DIC power delivery challenges.
  • Familiarity with die-package-system co-design and advanced packaging technologies such as 2.5D/3D integration.
  • Experience with transient and vector-based power analysis methodologies.
  • Knowledge of JEDEC standards and memory subsystem behavior.
  • Proven ability to mentor and develop junior engineers.

About the Company

Micron Technology

Makes memory and storage chips for AI and PCs

Micron Technology designs and manufactures memory and storage chips, mainly DRAM and NAND flash, used in data centers, PCs, phones, cars and industrial equipment. It is one of only three companies that make HBM, the stacked high-bandwidth memory placed beside processors in AI servers, and it is the largest memory chipmaker based in the United States. Unlike chip designers that outsource production, Micron runs its own fabs and assembly sites in the United States and across Asia. It earns money by selling chips, memory modules and solid-state drives to cloud providers, device makers and distributors. Micron was founded in 1978 and is headquartered in Boise, Idaho.

Company size
10,001+
Company stage
IPO
Headquarters
Boise, ID
Founded
1978

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