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Broadcom

Designs chips and software for data centers

ASIC Design Floorplan Engineer

Silicon & ASIC DesignConfirmed live in the last 24 hours
Full-timeFort Collins, CO, USAIn-person

About the Job

Requirements

  • Strong foundation in very large-scale integration (VLSI) design principles and application-specific integrated circuit (ASIC) physical design fundamentals.
  • In-depth experience with floorplanning, die partitioning, and hierarchical design.
  • Working knowledge of phase-locked loops (PLLs), clock networks, power delivery, and timing-critical structures.
  • Proven ability to drive performance, power, and area (PPA) optimization through innovative layout and planning strategies.
  • Strong experience with Tool Command Language (TCL) scripting and Linux environments.
  • A Bachelor of Science in Electrical Engineering or Computer Engineering with 12 or more years of relevant experience, or a Master of Science in Electrical Engineering or Computer Engineering with 10 or more years of relevant experience.
  • Excellent communication, organizational, and problem-solving skills.
  • Ability to work effectively with customers and cross-functional teams across global sites and time zones.
  • Skill in organizing and presenting large data sets and managing multiple priorities efficiently.
  • Ability to exercise independent judgment and strong engineering insight in defining methods, techniques, and evaluation criteria.

Responsibilities

  • Define and optimize top-level floorplan architecture, including die size estimation, hierarchy definition, and partitioning.
  • Drive macro placement, power grid design, clock distribution planning, pin placement, and feedthrough optimization.
  • Collaborate closely with register-transfer-level (RTL), timing, and packaging teams to balance performance, power, and area (PPA) targets.
  • Lead top-level timing closure, congestion analysis, and engineering change order (ECO) implementation to ensure clean tapeout readiness.
  • Coordinate with block owners and integration teams for smooth block-level to top-level convergence.
  • Support cross-functional design integration by providing guidance and technical support to internal and external partners.
  • Apply a deep understanding of block place-and-route (PnR), timing closure, physical verification, and current-density/electromigration (IR/EM) analysis to achieve signoff-quality results.
  • Contribute to design flow automation and methodology development for advanced process technologies.
  • Provide technical leadership, mentor others, and lead execution of new initiatives.

Desired Qualifications

  • Proficiency in Python, Perl, or Ruby.
  • Experience with Cadence or equivalent physical design tools.

About the Company

Broadcom

Designs chips and software for data centers

Broadcom designs chips and sells infrastructure software for the companies that run large data centers, telecom networks and corporate IT. Its custom AI processors, built with cloud companies, and its Ethernet switch chips move and process data inside the computer clusters that train AI models. The chip business also makes parts for broadband, wireless, storage and industrial equipment, sold to device makers and cloud operators, while VMware software lets businesses run private clouds and is sold by subscription. Broadcom took its current form in 2016, when Avago Technologies, formed in 2005 from Agilent's chip unit, bought Broadcom Corporation, and it is based in Palo Alto, California.

Company size
10,001+
Company stage
IPO
Headquarters
Palo Alto, CA
Founded
2005

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