Altera

FPGA and SoC provider with software

Lead Design Verification Engineer

Hardware Validation & TestingConfirmed live in the last 24 hours

Full-timeGeorge Town, Penang, MalaysiaNo salary listedIn-person

About the Job

Requirements

Candidate should have a Bachelor of Science, Master of Science, or PhD in Electrical or Computer Science Engineering or a related field, with 10+ years of technical experience.
Related technical experience should be in pre-silicon validation or verification.
Experience with OVM, UVM, SystemVerilog, and constrained-random verification methodologies is required.

Responsibilities

Perform functional logic verification of an FPGA to ensure the design meets specification requirements.
Develop FPGA verification plans, test benches, and the verification environment to ensure coverage against microarchitecture specifications.
Execute verification plans and define and run system simulation models to verify the FPGA design, analyze power and timing, and uncover bugs.
Replicate, identify root causes of, and debug issues in the pre-silicon environment; find and implement corrective measures to resolve failing tests.
Collaborate with FPGA architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.
Collaborate with systems and software engineers as needed to support integration testing of the FPGA.
Document test plans and drive technical reviews of plans and proofs with design and architecture teams.
Maintain and improve existing functional verification infrastructure and methodology.
Document, review, and execute verification strategy plans using different methodologies and techniques, such as gate-level simulation strategy and power patterns or power-aware simulations, to enable feature coverage against microarchitecture specifications.

Desired Qualifications

Experience in design verification, including developing, maintaining, and executing complex IPs and/or SoCs.
Experience with the complete verification life cycle, including verification architecture, test planning, execution, debugging, and coverage closure.
Experience developing validation test suites and driving continuous improvement in existing validation test suites and methodologies.
Experience in PCIe or UCIe PHY verification.

Job Details:

Job Description:

Performs functional logic verification of an FPGA to ensure design will meet specification requirements.
Develops FPGA verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications.
Executes verification plans and defines and runs system simulation models to verify the FPGA design, analyze power and timing, and uncover bugs.
Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests.
Collaborates with FPGA architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.
May also collaborate with systems and software engineers to support integration testing of the FPGA.
Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
Maintains and improves existing functional verification infrastructure and methodology.
Documents, reviews, and executes the verification strategy plan on different methodologies/techniques (e.g., gate-level-simulation strategy, power patterns/aware simulations) used to enable feature coverage as per the microarchitecture specifications.

Qualifications:

Minimal Qualification:

• Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 10+ years of technical experience.

• Related technical experience should be in/with: Pre Silicon Validation/Verification.

• OVM/UVM, System Verilog, constrained random verification methodologies.

Preferred Qualification:

• Design Verification with developing, maintaining, and executing complex IPs and/or SOCs.

• The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure).

• Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies.

• Experience in PCIe or UCIe PHY Verification.

Job Type:

Regular

Shift:

Shift 1 (Malaysia)

Primary Location:

Penang 15, Penang, Malaysia

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

About the Company

Altera

FPGA and SoC provider with software

Altera designs and manufactures FPGAs and SoCs, along with software tools for hardware design and deployment. Customers can configure these programmable chips after fabrication to fit specific applications, helping them reach market faster and optimize performance. The company differentiates itself by offering a broad configurable silicon platform and a dedicated design software suite as an independent provider after its separation from Intel. Its goal is to deliver high-performance, adaptable processing solutions for industries like automotive, aerospace, communications, AI, cloud, and edge computing.

Company size: Not listed
Company stage: IPO
Headquarters: San Jose, CA
Founded: 1983

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