Senior Staff Design Verification Engineer

Join d-Matrix and help build the future of AI inference. We’ve pioneered a memory-centric architecture that brings compute directly into memory, making AI faster, more energy efficient, and accessible on a global scale. From chips and software to rack-scale systems, our team is tackling some of AI infrastructure’s hardest challenges — and shipping breakthrough technology today. If you want to create what comes next and help make infinite inference possible, we’d love to hear from you.

Our culture is built on respect, collaboration, and direct communication. We value humility, we believe our different perspectives lead to better solutions, and we’re looking for people who are driven by execution and energized by hard problems.

Role Overview

d-Matrix is building a company and culture designed to last — one grounded in transparency, inclusiveness, and intellectual honesty, where continuous learning is part of the job. We've built the industry's first highly programmable in-memory computing architecture, applicable across a broad range of applications from cloud to edge. In this role, you'll work on a groundbreaking architecture alongside a highly experienced team that has a proven track record of building successful businesses. This is a unique opportunity to help shape a company at an early stage and grow into a future leader in an industry poised for global impact.

What You Will Do

• Develop and execute verification plans across the SoC/IP verification cycle, from architecture definition through tape-out and silicon bring-up

• Build and maintain UVM/OVM-based verification environments for complex ASIC/SoC designs

• Write and debug SystemVerilog testbenches, leveraging randomization, functional coverage, and assertion-based methodologies

• Drive root-cause analysis and debug of verification failures in close collaboration with design and architecture teams

• Define and track coverage closure goals to ensure comprehensive verification sign-off

• Partner cross-functionally with design, architecture, and physical design teams to align verification strategy with tape-out schedules

• Contribute to the evolution of verification methodology and infrastructure to support next-generation in-memory computing architectures

What You Will Bring

• BS in Electrical Engineering, Computer Science, or a related field with 12+ years of industry experience (MS preferred with 7+ years)

• Experience across the full SoC/IP verification cycle — from architecture through tape-out and bring-up

• Hands-on ASIC/SoC design verification test development and debug experience

• Fluency with SystemVerilog (randomization, constraints, coverage, assertions) and verification methodologies such as UVM/OVM/VMM

• Strong problem-solving skills and a passion for tackling complex technical challenges, particularly in the AI domain

Preferred Qualifications

• Experience with C/C++ and SystemC

• Track record leading the creation and implementation of multiple SoC verification environments and driving tape-out efforts

Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication, and a willingness to embrace challenges and learn together every day.

d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individuals interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of all applicants. Thank you for your understanding and cooperation.