NUVACORE

Designs high-performance, general-purpose CPU cores

Custom Memory Design Engineer - SRAMs and Register Files

Silicon & ASIC DesignConfirmed live in the last 24 hours

Full-time$140k - $200k /yr

About the Job

Requirements

Hold a Bachelor of Science or Master of Science degree and have 8 or more years of experience in custom memory circuit design, including SRAMs and/or register files.
Have hands-on transistor-level circuit design experience with combination cells, sequential logic in static and dynamic logic families, and memory arrays including bit cells, sense amplifiers, and decoders in advanced CMOS nodes.
Have deep knowledge of SPICE simulations, SRAM and register-file circuit margins, and special memory cell architectures.
Be proficient with industry-standard EDA tools for schematic design, layout, extraction, and characterization in custom memory design workflows.
Have a demonstrated track record of delivering production-level custom memory IP through tape-out, with silicon-validated PPA in high-volume products.
Have deep understanding of end-to-end custom memory signoff, including DRC/LVS/antenna, extraction, SPICE margins, static timing analysis, EM/IR, and characterization flows for timing, power, and noise.
Be well-versed in static timing analysis and Liberty/CCS library model development and correlation, including timing and power characterization for Functional and DFT modes.
Have strong communication and collaboration skills and be comfortable working directly with foundry, CAD, and physical design partner teams.

Responsibilities

Own schematic development and characterize custom memories, including SRAM and register files, to optimize PPA at advanced process nodes.
Supervise layout implementation, define macro floor planning and critical routing specifications, and drive physical design verification closure.
Own end-to-end memory IP signoff from schematic and layout through DRC/LVS/antenna, parasitic extraction, and characterization for timing, power, and noise in Liberty/CCS format across PVT corners, meeting target PPA commitments.
Partner with Foundry/PDK, CAD, Physical Design, RTL, and DFT teams to benchmark new process technology, validate IP on test chips, and co-optimize custom memories for downstream design PPA.
Collaborate with RTL to provide explicit custom memory functional specifications, timing behaviors, and state definitions that support accurate RTL modeling.
Define and drive adoption of tools, flows, and methodology, including characterization automation and compiler quality assurance, to improve design efficiency and establish team-wide best practices.

Desired Qualifications

Have substantial experience across the full embedded memory design flow, including architecture, circuit design, physical implementation, compiler automation, characterization, and timing/model generation.
Have experience designing and optimizing complex memory sub-blocks, including self-timed design tracking loops, read/write assist schemes, and power-gating headers, and translating PDK device characteristics into cell and bit-cell circuit decisions.
Have proven PPA-focused execution, including SRAM architecture trade-offs, critical-path modeling, full-cut analysis, and extensive Monte Carlo variation studies.
Have demonstrated experience converging on macro verification, including functional formal equivalence (LEC) and dynamic SPICE-versus-RTL co-simulation methods.
Have experience partnering directly with foundries on PDK bring-up and device co-optimization at leading-edge nodes.
Be proficient in Python, Perl, or TCL for design, characterization, and QA automation.
Have experience using Agentic AI tools for productivity and automation.

Salary Range: 140000 to 200000 (Currency: USD) (Pay period: per-year-salary)

At NUVACORE we're designing a new general-purpose CPU core for the sustained, intensive demands of AI infrastructure and agentic computing, not the workloads of the past. As a member of the CPU-specific custom circuit design team, you will enable the design to achieve the target PPA specifications for the product.

THE ROLE

As a Custom Memory Design Engineer, you will participate in the following :

Own schematic development and characterize custom memories (SRAM, register files) to optimize PPA at advanced process nodes.
Supervise layout implementation, defining macro floor planning, critical routing specifications, and driving physical design verification (PDV) closure.
Own end-to-end memory IP signoff: schematic and layout through DRC/LVS/antenna, parasitic extraction, and characterization (timing, power, and noise in Liberty/CCS format) across PVT corners, meeting target PPA commitments.
Partner with Foundry/PDK, CAD, Physical Design, RTL and DFT teams to benchmark new process technology, validate IP on testchips, and co-optimize custom memories for downstream design PPA.
Collaborate closely with RTL, providing explicit custom memory functional specifications, timing behaviors, and state definitions to support accurate RTL modeling.
Define and drive adoption of Tools, Flows, and Methodology (TFM) — including characterization automation and compiler QA — to raise design efficiency and set team-wide best practices.

MINIMUM QUALIFICATIONS

Hold a BS or MS degree with 8+ years of experience in custom memory circuit design : SRAMs, and/or Register files.
Hands-on transistor-level circuit design experience with combo cells, sequential logic in static/dynamic logic families, as well as memory arrays — bit cells, sense amps, decoders — in advanced CMOS nodes.
Deep knowledge of SPICE simulations, SRAMs / Register File circuit margins, and special memory cell architectures.
Proficient with industry-standard EDA tools for schematic, layout, extraction, and characterization, applied to custom memory design workflows.
Demonstrated track record delivering production-level custom memory IP through tape-out, with silicon-validated PPA in high-volume products.
Deep understanding of end-to-end signoff for custom memories — DRC/LVS/antenna, extraction, SPICE margins, STA, EM/IR — and characterization flows spanning timing, power, and noise.
Well-versed in STA and Liberty/CCS lib model development and correlation, including timing and power characterization for both Functional and DFT (Design for Test) modes.
Strong communication and collaboration skills, comfortable working directly with foundry, CAD, and physical design partner teams.

REQUIREMENTS — PREFERRED

Substantial experience across the full embedded memory design flow — architecture, circuit design, physical implementation, compiler automation, characterization, and timing/model generation.
Experience designing and optimizing complex memory sub-blocks (self timed design tracking loops, read/write assist schemes, power-gating headers) and translating PDK device characteristics into cell/bit-cell circuit decisions.
Proven PPA-focused execution, including SRAM architecture trade-offs, critical-path modeling, full-cut analysis, and extensive Monte Carlo variation studies.
Demonstrated experience converging on macro verification, including functional formal equivalence (LEC) and dynamic SPICE-versus-RTL co-simulation (cosim) methods.
Experience partnering directly with foundries on PDK bring-up and device co-optimization (DTCO) at leading-edge nodes.
Proficient in Python, Perl, or TCL to build and improve design, characterization, and QA automation.
Experience using Agentic AI tools for productivity and automation.

The next great CPU won't build itself. We’re assembling a world-class team across every layer of CPU development, from architecture and design to verification, physical implementation, software, infrastructure, and product delivery. Every discipline matters, and every person has the opportunity to help shape the technology from the ground up.

About the Company

NUVACORE

Designs high-performance, general-purpose CPU cores

Nuvacore designs high-performance, general-purpose CPU cores built from the ground up to meet AI-focused workloads in data centers and advanced systems. It offers cores as either IP for chip developers or finished chips, optimized for speed and area efficiency to handle continuous, long-running tasks. The team combines veterans from Nuvia, Apple, and Arm, focusing on agentic computing rather than specialized accelerators to differentiate from competitors. The goal is to deliver scalable, reliable CPUs that provide high throughput for large-scale AI workloads and continuous computing tasks.

Company size: 51-200
Company stage: Not listed
Total funding: Not listed
Headquarters: San Jose, CA
Founded: 2026

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