S

SiTime

Fabless MEMS timing solutions provider

Principal FPGA Design Engineer

Silicon & ASIC DesignUpdated on Nov 14
Full-time$148.3k - $203.9k /yrIn-person

About the Job

Requirements

  • A Master of Science degree in Electrical Engineering, Computer Engineering, or a related field is required.
  • At least 10 years of hands-on experience in FPGA architecture and development using Xilinx, Intel/Altera, or similar platforms is required.
  • Deep expertise in Verilog or VHDL, simulation tools such as ModelSim or Vivado, and scripting with Python or TCL is required.
  • A proven track record designing systems with low jitter, low phase noise, and high signal fidelity is required.
  • A strong understanding of timing analysis, clock domain crossing, and high-speed interfaces such as PCIe, DDR, and SERDES is required.
  • Experience with lab bring-up, debugging tools such as logic analyzers and oscilloscopes, and test automation is required.
  • Demonstrated leadership in driving cross-functional initiatives and delivering complex technical programs is required.

Responsibilities

  • Architect and implement scalable FPGA solutions for internal hardware platforms used in MEMS timing product testing.
  • Lead cross-functional technical initiatives involving CMOS design, MEMS design, systems and test engineering, validation, and production teams.
  • Define and drive system-level requirements, ensuring alignment across hardware, software, and test domains.
  • Own the full FPGA lifecycle, including architecture, RTL design, simulation, synthesis, timing closure, and bring-up.
  • Develop reusable IP blocks and maintain a modular, maintainable FPGA infrastructure.
  • Champion design reviews, documentation standards, and continuous improvement practices.
  • Provide technical leadership and mentorship to junior engineers and influence strategic direction across multiple programs.
  • Act as a key technical liaison between engineering, product, and operations teams to ensure seamless integration and execution.

Desired Qualifications

  • Experience in MEMS or timing product domains.
  • Familiarity with hardware/software co-design and embedded systems.
  • Exposure to production test environments and ATE systems.
  • Experience presenting technical strategies and outcomes to executive leadership.

About the Company

SiTime

Fabless MEMS timing solutions provider

SiTime designs MEMS-based timing solutions (oscillators, network synchronizers, and jitter cleaners) as a fabless semiconductor company. MEMS resonators on silicon replace quartz to generate precise clocks and synchronize networks, with manufacturing handled by third-party foundries. The approach offers smaller size, lower power consumption, and better temperature stability, supported by scalable, design-focused development rather than in-house fabrication. Its goal is to expand MEMS timing adoption across automotive, industrial, IoT, mobile, aerospace, and telecom markets worldwide.

Company size
501-1,000
Company stage
IPO
Headquarters
Santa Clara, CA
Founded
2005

Recently Posted Jobs

Explore more opportunities at SiTime

See more jobs